Compact E-fuse With Vertical Stack For Nanowire CMOS

The E-fuse structure transitions from a planar two-dimensional layout to a three-dimensional vertical stack configuration. Multiple semiconductor layers are stacked vertically with metal semiconductor alloy portions formed at different heights, creating a compact vertical architecture that reduces the horizontal footprint while maintaining fuse functionality through the vertical dimension.

The E-fuse structure employs a nested arrangement where metal semiconductor alloy portions are embedded within and between semiconductor layers. The alloy portions are positioned at specific vertical levels within the stacked structure, creating a nested configuration that maximizes space utilization and reduces the overall area occupied by the fuse.

The multilayered semiconductor stack structure serves multiple functions: it provides the fuse functionality through the metal semiconductor alloy portions while also being compatible with nanowire CMOS device fabrication processes. The same epitaxial growth and patterning techniques used for nanowire transistors are applied to form the E-fuse, enabling universal process compatibility and facilitating integration into nanowire CMOS circuits.

By transitioning to a vertical stacked architecture, the E-fuse achieves compact footprint dimensions that are compatible with scaled nanowire CMOS technology. The vertical stacking allows the fuse to occupy minimal planar area while maintaining adequate functional dimensions in the vertical direction, thereby adapting to the area constraints of advanced nanowire processes.

The semiconductor layers are prepared in advance through epitaxial growth as a complete multilayered stack with predetermined layer sequences and compositions. This preliminary formation of the stacked structure before patterning allows subsequent processing steps to simply define the fuse regions by removing or modifying specific portions, rather than requiring complex simultaneous patterning of multiple layers.

The continuous semiconductor layers are segmented into discrete portions corresponding to different functional regions of the E-fuse. The patterning process divides the multilayered stack into first, second, third, and fourth semiconductor portions, with metal semiconductor alloy portions formed in specific segments. This segmentation allows independent control and processing of different fuse regions while maintaining overall structure integrity.