Compact EEPROM Cell Layout With Dual-Thickness Gate Dielectric
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Solution Overview
Problem
EEPROM memory cells are bulkier due to the need for robust access transistors to handle high programming voltages, limiting their compactness and density, especially below a storage density ceiling of 8 to 16 Mb.
Innovation Solution
A memory device with a state transistor and an access transistor, where the floating gate has a dielectric layer with varying thicknesses, allowing for a narrower injection window and enabling the access transistor to be more compact by avoiding high voltages, and using a configuration where the access transistor is coupled to a source line and the state transistor to a bit line, reducing the stress on the access transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If robust access transistors are used to handle high programming voltages, then the transistors can transmit high voltages (13 to 15 volts) for programming operations, but the memory cell size increases and density decreases
Solution Approach 1:
The patent divides the memory cell into two separate transistors: an access transistor that handles voltage transmission and a state transistor that performs the actual programming. This segmentation allows the access transistor to be optimized for voltage handling while the state transistor is optimized for compactness, resolving the contradiction between robustness and size.
Solution Approach 2:
Instead of having the access transistor directly connected to the floating gate (which would require it to be robust and large), the patent inverts the connection by having the state transistor's drain connected to the bit line and its source connected to the access transistor's drain. This allows the access transistor to operate at lower voltages while still enabling high-voltage programming through the state transistor.
2Ease of manufacture
If the dielectric layer under the floating gate has uniform thickness, then fabrication is simpler, but the injection window is wider causing increased leakage and wear
Solution Approach 1:
The patent applies local quality by creating a non-uniform dielectric layer thickness: a first thickness in the channel region and a second, greater thickness in the drain region. This local variation reduces the injection window width, thereby decreasing electron tunneling, leakage current, and wear while remaining compatible with standard fabrication processes.
3Power
If EEPROM memory cells use traditional configuration with access transistor connected to bit line, then high programming voltage can be applied, but the access transistor must be large and robust to handle the voltage
Solution Approach 1:
The patent inverts the traditional connection by having the state transistor's drain connected to the bit line rather than the access transistor's drain. This allows high programming voltage to be applied to the state transistor for effective programming, while the access transistor operates at lower voltages and can be made smaller and less complex.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for more compact EEPROM memory cells while managing high write voltages, reducing leakage and wear, and enabling smaller access transistors, thus improving memory cell density without increasing fabrication complexity.
Implementation Method 1
During the erasure, a positive high erasing voltage is applied to the control gate of the state transistor, injecting, via Fowler-Nordheim effect, an electron charge into the floating gate
Implementation Method 2
The state transistor allows a charge representative of a logic datum to be stored in a non-volatile manner in its floating gate
Implementation Method 3
a positive high programming voltage is applied to the drain of the state transistor, via the bit line and through the access transistor
Data Source
AI summary
An EEPROM memory integrated circuit includes memory cells arranged in a memory plane. Each memory cell includes an access transistor in series with a state transistor. Each access transistor is coupled, via its source region, to the corresponding source line and each state transistor is coupled, via its drain region, to the corresponding bit line. The floating gate of each state transistor rests on a dielectric layer having a first part with a first thickness, and a second part with a second thickness that is less than the first thickness. The second part is located on the source side of the state transistor.