Compact eFuse Array Using Shared NMOSFETs and Diodes
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Solution Overview
Problem
Conventional electrically programmable fuse (eFuse) arrays face challenges with high programming voltage requirements, leading to large device sizes and reliability issues due to the need for high voltage bit line operations and large peripheral circuits, particularly at the 28 nm technology node.
Innovation Solution
The eFuse cell array incorporates a polysilicon material with a silicide layer and a PNP bipolar transistor, along with shared NMOSFETs and a matrix arrangement of eFuse cells, which reduces device size by utilizing a shared NMOSFET for each row and write bit lines, and includes diodes to manage voltage and prevent adjacent cell disturbance during operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage programming is used to program eFuse, then the eFuse can be programmed, but the device area increases due to large peripheral circuits
Solution Approach 1:
Multiple eFuse cells share common bit lines and NMOS transistors, merging previously separate high-voltage signal paths into shared infrastructure that serves multiple cells simultaneously
Solution Approach 2:
The bit lines and NMOS transistors serve dual purposes: they are shared across multiple eFuse cells for programming operations, and the same infrastructure supports both high-voltage programming and low-voltage read operations
2Reliability
If high voltage bit line operations are used for eFuse programming, then programming can be achieved, but reliability decreases due to adverse effects on total number of operations
Solution Approach 1:
The eFuse array is divided into rows and columns with dedicated bit lines for each column, allowing selective activation of specific cells while sharing infrastructure, which isolates high-voltage stress to only the actively programmed cells
Solution Approach 2:
NMOS transistors act as intermediary switches that control the flow of high-voltage programming current through selected eFuse cells, protecting the overall array by isolating high-voltage operations to specific cells rather than exposing the entire bit line network
3Reliability
If conventional eFuse array with HVNMOS is used, then programming voltage can be achieved, but the area is dominated by eFuse cell size for high-capacity arrays
Solution Approach 1:
Adjacent eFuse cells share common bit lines and NMOS transistors, merging previously separate high-voltage signal paths into shared infrastructure that serves multiple cells simultaneously
Solution Approach 2:
The bit lines and NMOS transistors serve dual purposes: they are shared across multiple eFuse cells for programming operations, and the same infrastructure supports both high-voltage programming and low-voltage read operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in a compact eFuse cell array with improved reliability and reduced size, allowing for efficient programming and reading operations while minimizing the impact of high voltage on device area and operation count.
Implementation Method 1
An eFuse is an electrically programmable memory device whose resistance can be changed by passing an electric current through it. Programmed eFuses are electrically high resistance, while unprogrammed eFuses remain in a low resistance state.
Implementation Method 2
The programming current can cause the silicide layer to redistribute and be broken, resulting in the high resistance state.
Implementation Method 3
Each eFuse cell may include a PNP bipolar transistor. In the PNP bipolar transistor the first diode may be formed by a first PN junction of the bipolar transistor, the second diode may be formed by a second PN junction of the bipolar transistor
Implementation Method 4
The plurality of electrical fuse (eFuse) cells may comprise n by m eFuse cells arranged in an n by m matrix with n rows and m columns, n and m being integers. The memory device may further include n shared NMOSFETs and m write bit lines
Data Source
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AI summary
An electrical fuse (eFuse) array includes eFuse cells arranged in multiple rows and columns. Each eFuse cell has an eFuse, a first diode, and a second diode coupled to an internal node, each eFuse cell further having first, second, and third terminals coupled, respectively, to the first diode, the second diode, and the eFuse. The eFuse array further includes a shared NMOSFET for each of the multiple rows, with a drain coupled to the third terminal of each of the plurality of eFuse cells in that row and a gate coupled to a word line. Each column includes a write bit line coupled to the second terminal of each of the eFuse cells in that column, and a read bit line coupled to the first terminal of the eFuse cell.