Compact FinFET OTP Cell Using Vertical Third Gate
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Solution Overview
Problem
Current memory designs for semiconductor devices face challenges such as program disturb/interference, large cell size, and circuit design hazards due to floating voltages in one-time programmable (OTP) and multiple-time programmable (MTP) memory cells, particularly in high-density anti-fuse twin-gate isolation (TGI) OTP memory cells and fin-type field effect transistor (FinFET) dielectric resistive random-access memory (RRAM) cells.
Innovation Solution
The method involves forming compact FinFET and fully depleted silicon on insulator (FDSOI) OTP/MTP cells by creating a substrate with a buried oxide layer, forming fins with gaps, and placing gates perpendicular to the fins with additional third gates that overlap the fins and connect to the buried oxide layer, along with source/drain regions and bit lines, to reduce cell size and mitigate program disturb/interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the length of gates 103 is increased for proper p+ implant alignment, then manufacturing precision is improved, but device complexity and cell size increase
Solution Approach 1:
The patent introduces a vertical dimension by forming the third gate perpendicular to the substrate and intersecting the first and second gates in three-dimensional space. This allows the third gate to contact the BOX layer through the gap between the first and second gates, providing a new spatial dimension for electrical connection that reduces the need for large lateral dimensions while maintaining proper implant alignment
Solution Approach 2:
The third gate is positioned within the vertical space created by the gap between the first and second gates, effectively nesting the third gate structure within the existing gate configuration. This nested arrangement allows the third gate to extend vertically through the gap to contact the BOX layer without increasing the lateral footprint of the cell
2Ease of manufacture
If the space between gates 103 is increased for p+ doped S/D region formation, then ease of manufacture is improved, but device complexity and cell size increase
Solution Approach 1:
The third gate extends vertically through the gap between the first and second gates to contact the BOX layer, utilizing the vertical dimension to provide the necessary electrical connection and structural support. This eliminates the need to increase the lateral space between gates for S/D region formation, as the third gate's vertical extension provides the required functionality within the existing lateral footprint
Solution Approach 2:
The gate structure is segmented into three distinct gates: the first and second gates forming the primary horizontal structure, and the third gate providing vertical connectivity through the gap. This segmentation allows each gate to perform its specific function independently, with the third gate specifically addressing the BOX layer contact requirement without interfering with the S/D region formation between the first and second gates
3Productivity
If cell size is reduced for higher packing density, then productivity is improved, but program disturb/interference increases
Solution Approach 1:
The third gate extends vertically through the gap between the first and second gates to contact the BOX layer, utilizing the vertical dimension to provide electrical isolation and control. This three-dimensional structure allows for reduced lateral cell dimensions while maintaining adequate electrical separation to prevent program disturb and interference, thereby enabling higher packing density without sacrificing reliability
Solution Approach 2:
The third gate acts as an intermediary structure that vertically connects the BOX layer to the gate structure, providing electrical control and isolation. This intermediary element enables compact cell design by mediating the electrical interactions between the first and second gates and the BOX layer, preventing unwanted coupling and program disturb while allowing smaller lateral dimensions for higher density
Data Source
AI summary
Methods of forming a compact FinFET OTP/MTP cell and a compact FDSOI OTP/MTP cell and resulting devices are provided. Embodiments include providing a substrate having a BOX layer; forming fins on the BOX layer with a gap in between; forming first and second gates, laterally separated, over and perpendicular to the fins; forming at least one third gate between the first and second gates and contacting the BOX layer through the gap, each third gate overlapping an end of a fin or both fins; forming a S/D region in each of the fins adjacent to the first and second gates, respectively, remote from the at least one third gate; utilizing each of the first and second gates as a WL; utilizing each third gate as a SL or connecting a SL to the S/D region; and connecting a BL to the S/D region or the at least one third gate.