Compact LPHDR Arithmetic Elements for Higher Chip Throughput
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Solution Overview
Problem
Conventional computing architectures inefficiently utilize transistors due to a focus on high precision arithmetic, limiting the ability to harness the full computing power of silicon chips, despite the availability of greater transistor counts.
Innovation Solution
Implementing low precision high dynamic range (LPHDR) processing elements that perform arithmetic operations using logarithmic representations or analog methods, allowing for a greater number of computing elements to be fit into a given area, thereby increasing computational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional high precision arithmetic processing elements are used, then computational accuracy is maintained, but the number of processing elements that can be integrated on a chip is limited
Solution Approach 1:
The patent changes the precision parameter of arithmetic operations from conventional high precision (e.g., 32-bit or 64-bit floating point) to low precision (e.g., 8-bit or 16-bit fixed point or low precision floating point). This parameter change allows significantly more processing elements to be integrated on a single chip, increasing computational throughput while maintaining adequate accuracy for many applications.
Solution Approach 2:
The patent segments the computational task into multiple lower precision operations that can be performed in parallel by numerous simple processing elements, rather than using fewer complex high precision elements. This segmentation enables massive parallelism and higher overall computational productivity.
2Power
If the number of transistors is increased to provide more computing power, then theoretical computing power grows exponentially, but the ability of software to utilize this hardware power remains limited
Solution Approach 1:
The patent changes the operational parameters of processing elements to low precision arithmetic, which dramatically reduces the resource requirements per processing element. This enables the integration of thousands or millions of processing elements on a single chip, allowing software to effectively utilize the exponential growth in available transistors for practical computational tasks.
Solution Approach 2:
The patent uses many simple, identical, low precision processing elements that can be mass-produced and densely packed on a chip. These numerous simple elements collectively provide the computing power that would otherwise require far fewer complex high precision elements, thereby improving software utilization efficiency.
3Productivity
If low precision arithmetic operations are used, then more processing elements can be integrated on a chip, but the precision of computational results decreases
Solution Approach 1:
The patent segments computational tasks into multiple independent or loosely coupled operations that can be performed by low precision processing elements. By dividing the overall computation into many small steps that can be executed in parallel, the system achieves high processing element density while maintaining adequate overall accuracy through the cumulative effect of many precise parallel operations.
Solution Approach 2:
The patent carefully selects and adjusts the precision parameters of low precision arithmetic operations to match the specific requirements of target applications. For many scientific computing, machine learning, and signal processing applications, 8-bit or 16-bit precision provides sufficient accuracy while enabling massive integration of processing elements.
Data Source
AI summary
A processor or other device, such as a programmable and/or massively parallel processor or other device, includes processing elements designed to perform arithmetic operations (possibly but not necessarily including, for example, one or more of addition, multiplication, subtraction, and division) on numerical values of low precision but high dynamic range (“LPHDR arithmetic”). Such a processor or other device may, for example, be implemented on a single chip. Whether or not implemented on a single chip, the number of LPHDR arithmetic elements in the processor or other device in certain embodiments of the present invention significantly exceeds (e.g., by at least 20 more than three times) the number of arithmetic elements, if any, in the processor or other device which are designed to perform high dynamic range arithmetic of traditional precision (such as 32 bit or 64 bit floating point arithmetic).