Compact Arithmetic Elements Using LPHDR Precision for Transistor Efficiency
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Solution Overview
Problem
Conventional CPU architectures are inefficient in utilizing transistors for computing, as they are designed to provide high precision arithmetic, leading to underutilization of the vast computing power available in modern silicon microprocessors.
Innovation Solution
The development of processors that incorporate low precision high dynamic range (LPHDR) processing elements, which perform arithmetic operations with lower precision but higher dynamic range, allowing for a greater number of operations per unit of time or power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional CPU architectures use high precision arithmetic operations, then calculation accuracy is improved, but the number of operations per unit time decreases
Solution Approach 1:
The patent changes the precision parameter of arithmetic operations from conventional high precision (e.g., 64-bit floating point) to low precision (e.g., 8-bit or 16-bit fixed point or floating point). This parameter change allows significantly more operations to be performed per clock cycle, improving throughput for applications where approximate results are acceptable.
Solution Approach 2:
The patent segments the computing workload into tasks that can tolerate low precision and those requiring high precision. By dividing the computational domain, low precision operations can be applied to appropriate tasks (such as graphics rendering, machine learning inference, and scientific simulations) to achieve high operation counts while maintaining adequate accuracy.
2Measurement precision
If conventional CPU architectures use high precision arithmetic operations, then calculation accuracy is improved, but power consumption increases
Solution Approach 1:
The patent changes the precision parameter to reduce power consumption. Low precision arithmetic operations require fewer transistors, smaller data paths, and less complex logic circuits, directly reducing dynamic and static power consumption. This is particularly beneficial for mobile devices and data centers where energy efficiency is critical.
Solution Approach 2:
The patent employs low precision arithmetic units that are computationally 'cheaper' in terms of power and area. These simplified processing elements consume less energy per operation, enabling higher operation counts within the same power budget, effectively trading precision for energy efficiency.
3Measurement precision
If conventional CPU architectures use high precision arithmetic operations, then calculation accuracy is improved, but transistor utilization efficiency decreases
Solution Approach 1:
The patent changes the arithmetic precision parameter to optimize transistor utilization. Low precision operations enable more arithmetic units to be packed into the same silicon area, increasing the density of computational elements and improving overall transistor utilization efficiency.
Solution Approach 2:
The patent segments the processor architecture into multiple low precision arithmetic units that can operate in parallel. This segmentation allows better utilization of available transistors by distributing work across many simple units rather than fewer complex units, achieving higher overall throughput and resource utilization.
Data Source
AI summary
A processor or other device, such as a programmable and/or massively parallel processor or other device, includes processing elements designed to perform arithmetic operations (possibly but not necessarily including, for example, one or more of addition, multiplication, subtraction, and division) on numerical values of low precision but high dynamic range (“LPHDR arithmetic”). Such a processor or other device may, for example, be implemented on a single chip. Whether or not implemented on a single chip, the number of LPHDR arithmetic elements in the processor or other device in certain embodiments of the present invention significantly exceeds (e.g., by at least 20 more than three times) the number of arithmetic elements, if any, in the processor or other device which are designed to perform high dynamic range arithmetic of traditional precision (such as 32 bit or 64 bit floating point arithmetic).