High-Speed Compact Look-Up Table with Input Select and Registers
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Solution Overview
Problem
Conventional reconfigurable logic devices like FPGAs suffer from larger die area, higher power consumption, and lower speed, while ASICs have high non-recurring engineering costs and limited flexibility.
Innovation Solution
A reconfigurable hardware device and architecture utilizing a look-up table with programmable memory cells and multiplexers in a tree-like structure, including inverters and buffers, to provide a compact and efficient computing solution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional reconfigurable logic devices like FPGA are used, then flexibility is improved, but die area increases
Solution Approach 1:
The invention segments the reconfigurable logic into compact lookup tables (LUTs) with integrated multiplexers and registers. Each LUT is a self-contained unit that can be tightly packed, reducing overall die area while maintaining reconfigurability through the programmable nature of individual LUTs.
Solution Approach 2:
The invention merges multiple functions into unified structures: lookup tables combine memory cells with multiplexers in a single compact unit, registers are integrated within the LUT fabric, and routing resources are shared across the array. This consolidation eliminates redundant components and reduces total die area.
2Adaptability or versatility
If conventional reconfigurable logic devices like FPGA are used, then flexibility is improved, but power consumption increases
Solution Approach 1:
By segmenting the device into small, independent LUTs, the invention enables selective activation of only the reconfigurable elements needed for a given application. Unused LUTs can remain inactive, reducing overall power consumption while maintaining flexibility where required.
Solution Approach 2:
The integration of multiplexers and registers within the LUT structure eliminates separate control logic and reduces the number of independent power domains. This merging reduces switching activity and overall power consumption compared to conventional FPGAs with separate routing and logic resources.
3Adaptability or versatility
If conventional reconfigurable logic devices like FPGA are used, then flexibility is improved, but speed decreases
Solution Approach 1:
The fine-grained segmentation into small LUTs reduces the critical path length within each logic unit. Signals traverse shorter distances within compact LUTs compared to larger FPGA logic blocks, enabling higher operating frequencies while maintaining overall system flexibility.
Solution Approach 2:
By merging memory cells, multiplexers, and registers into tightly integrated LUT structures, the invention reduces inter-component signal propagation delays. The compact internal routing within unified LUT structures eliminates the need for long external interconnects, improving speed.
4Area of stationary object
If ASIC is used, then die area and power consumption are reduced, but flexibility decreases
Solution Approach 1:
The invention introduces dynamic reconfigurability into an otherwise compact ASIC-like structure. The programmable LUTs allow the hardware logic to be dynamically reconfigured for different applications, providing flexibility similar to FPGAs while maintaining the small die area characteristic of ASICs.
Data Source
AI summary
Reconfigurable device components such as look up tables (LUT), D-flip flop registers and internal switch designs for programmable array of logic (PLA), programmable logic array (PLA), programmable logic device (PLD), complex PLD (CPLD), field programmable gate arrays (FPGAs), eASIC, structured ASIC, embedded FPGAs, and other programmable hardware devices are provided.