Compact Non-Volatile Memory Cell Layout for OTP and MTP
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Solution Overview
Problem
Conventional non-volatile memories, both one-time-programmable (OTP) and multiple-time-programmable (MTP), suffer from relatively large device sizes.
Innovation Solution
A non-volatile memory structure is designed with specific doped regions of opposite conductivity types and a silicide layer, allowing for compact device fabrication using a CMOS process with minimal additional masks, enabling one-time or multiple-time programmability based on gate dielectric material choice.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
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If conventional OTP or MTP memory structures are used, then non-volatile memory functionality is achieved, but device size becomes relatively large
Solution Approach 1:
The patent utilizes the vertical dimension by positioning the first doped region beneath the gate dielectric layer while the second doped region is positioned adjacent to it in the active region. This three-dimensional arrangement of doped regions (first doped region at a deeper level, second doped region at a shallower adjacent level) enables compact memory cell design without sacrificing functionality, effectively reducing device footprint by exploiting spatial dimensions beyond the traditional planar layout
Solution Approach 2:
The structure embeds the first doped region within the vertical profile of the gate dielectric layer, while the second doped region is positioned adjacent to it. This nested spatial arrangement allows multiple functional regions to occupy overlapping or adjacent spatial volumes, maximizing space utilization and reducing the overall device size while maintaining distinct electrical functions for each doped region
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The structure achieves a compact non-volatile memory element with programmable gate dielectric layers, providing either one-time or multiple-time programming capabilities while maintaining a reduced device size.
Implementation Method 1
The first doped region has a first conductivity type, and the second doped region has a second conductivity type opposite to the first conductivity type
Data Source
AI summary
Structures for a non-volatile memory and methods of forming such structures. A gate electrode and a gate dielectric layer are formed over an active region with the gate dielectric layer between the gate electrode and the active region. A first doped region is formed in the active region, a second doped region is formed in the active region, and a source line is coupled to the second doped region. The first doped region is positioned in the active region at least in part beneath the gate dielectric layer, and the second doped region is positioned in the active region adjacent to the first doped region. The first doped region has a first conductivity type, and the second doped region has a second conductivity type opposite to the first conductivity type.