Compact 2T2C Memory Structure with Shared Wells
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Solution Overview
Problem
Current two-bit memory devices are larger in size due to the combination of two one-bit 2T1C memory devices, making them less desirable for compact consumer electronic products.
Innovation Solution
A memory structure is designed with a substrate featuring multiple well regions of different conductivity types, where gate structures extend over these well regions, allowing for a more compact 2T2C memory device configuration with shared well regions and conductive regions, enabling a higher cell density and reduced size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two one-bit 2T1C memory devices are coupled together to form a two-bit memory device, then the memory capacity is increased, but the device size becomes larger
Solution Approach 1:
The patent merges two one-bit memory devices into a single two-bit memory device by sharing common components. Specifically, the first and second memory devices share a common substrate, common well regions (first well region 1041, second well region 1042, third well region 1043), and common gate structures (first gate structure 1201, second gate structure 1202), thereby reducing the overall device area while maintaining double the memory capacity.
Solution Approach 2:
The common well regions and gate structures serve multiple functions simultaneously. The first well region 1041 and third well region 1043 both serve as source/drain regions for different transistors in the two memory devices. The first gate structure 1201 and second gate structure 1202 are shared control elements that manage both memory cells, allowing a single physical structure to perform the functions of two separate memory devices.
2Reliability
If a traditional 2T2C memory device configuration is used, then the memory function is achieved, but the cell size is large and cell density is low
Solution Approach 1:
The patent implements a nested configuration where the first and second memory devices are embedded within a shared substrate structure. The well regions 1041-1043 and gate structures 1201-1202 are nested such that they serve both memory devices simultaneously, with the second memory device 100b sharing the same physical infrastructure as the first memory device 100a, thereby reducing the area per cell.
Solution Approach 2:
The patent transitions from a planar arrangement of separate memory devices to a three-dimensional integrated structure where well regions and gate structures are arranged in multiple layers and dimensions. The gate structures extend over multiple well regions in a spatial configuration that optimizes area utilization, effectively packing more functionality into a smaller footprint by utilizing vertical and lateral spatial dimensions efficiently.
Data Source
AI summary
A memory structure may be provided, including a substrate, and a first well region, a second well region, and a third well region arranged within the substrate, where the first well region and the third well region may have a first conductivity type, and the second well region may have a second conductivity type different from the first conductivity type, and where the second well region may be arranged laterally between the first well region and the third well region. The memory structure may further include a first gate structure and a second gate structure arranged over the second well region. The first gate structure may extend over the third well region and the second gate structure may extend over the first well region.