Compact Read Only Memory Cell Ground Line Sharing
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Solution Overview
Problem
Existing read only memory cells face limitations in size reduction due to minimum area requirements for conductors and the inability to physically share a ground line between adjacent cells, which restricts their compactness.
Innovation Solution
A method is introduced to connect a ground line to a first conductor and share it between adjacent columns, while connecting a bit line to a second conductor and providing a word line to the gate of a transistor, allowing for efficient programming of logic zero and logic one states by electrically connecting the drain and source to the bit line and ground line respectively, thereby meeting design rules and reducing physical size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the minimum area requirement for first conductor is adhered to in traditional design, then design rules are met, but the read only memory cell size is limited and cannot be reduced
Solution Approach 1:
The ground lines of adjacent memory cells are merged into a single shared ground line. Instead of providing separate ground lines for each cell, the patent combines the ground connections of adjacent cells, allowing them to share the same ground path. This merging eliminates redundant ground line areas while maintaining electrical connectivity and design rule compliance, directly resolving the contradiction between meeting minimum conductor area requirements and reducing overall cell size.
Solution Approach 2:
The shared ground line serves multiple functions simultaneously - it acts as the ground connection for multiple adjacent memory cells at once. This multi-functional ground line structure allows a single conductor to fulfill the grounding requirement for several cells, thereby reducing the total conductor area needed per cell while still meeting design rules for each individual cell's electrical connectivity.
2Reliability
If separate ground lines are provided for adjacent columns, then each cell meets design rules, but physical sharing is prevented and cell size increases
Solution Approach 1:
Adjacent memory cells are designed to share a common ground line structure. The ground lines from multiple cells are merged into a single physical conductor that serves all adjacent cells simultaneously. This merging maintains reliable electrical connectivity for each cell while enabling physical sharing, thereby reducing the overall area occupied by ground conductors in the memory array.
Data Source
AI summary
A method of manufacturing a read only memory cell includes connecting electrically a drain of the transistor to the bit line with a first conductor and a via. The method also includes generating a logic zero at a source of the transistor by electrically connecting the source of the transistor to a ground line with the first conductor. Further, the method includes, programming the read only memory cell to logic zero. A method of manufacturing a read only memory cell includes connecting electrically a drain of the transistor to the bit line with a first conductor and a via. The method also includes, connecting electrically a source of the transistor to the drain with the first conductor. Further, the method includes programming the read only memory cell to logic one.