Compact Routing for Hierarchical Integrated Circuits
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Solution Overview
Problem
Conventional integrated circuit design routing approaches often result in non-straight routings for upper level blocks due to unconstrained consumption of routing resources during the routing of lower level blocks, leading to difficulties in generating effective routing plans.
Innovation Solution
The technique involves constraining routing resources during the routing of lower level blocks to minimize the number of tracks used, allowing for the reuse of freed tracks for upper level blocks, and iteratively relaxing constraints to achieve a compact and straight routing plan by employing a process that determines the minimal number of tracks needed and intelligently inserts routing blockage constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If routing resources are unconstrained during lower level block routing, then routing completion for lower level blocks is achieved, but routing resources are consumed leaving insufficient resources for upper level blocks resulting in non-straight routings
Solution Approach 1:
The patent applies preliminary action by determining the minimal number of tracks required for lower level block routing before actually performing the routing. This allows routing blockage constraints to be inserted in advance, preventing excessive consumption of routing resources during lower level routing, thereby preserving resources for upper level blocks and enabling straighter routings at higher levels.
2Ease of operation
If routing blockage constraints are inserted to limit track usage in lower level blocks, then routing resources are preserved for upper level blocks, but routing complexity increases due to iterative constraint relaxation
Solution Approach 1:
The patent applies dynamics by implementing an iterative process where routing blockage constraints are initially inserted to limit track usage, then selectively relaxed based on routing progress and success. The system dynamically adjusts constraints by attempting routing with relaxed blockages and evaluating results, allowing the routing process to adaptively balance resource preservation with routing completeness.
3Shape
If minimal number of tracks is determined and constraints are inserted, then straight routings are enabled for upper level blocks, but additional processing steps are required to determine minimal tracks and manage constraints
Solution Approach 1:
The patent performs preliminary determination of the minimal number of tracks required for lower level block routing before inserting routing blockage constraints. This advance planning enables the system to preserve specific tracks for upper level blocks, facilitating straighter routings at higher levels while managing the additional processing through a structured, multi-step approach.
Data Source
AI summary
Techniques for compacting routing in lower level blocks to free routing resources for upper level blocks are disclosed. In some embodiments, a specification of a hierarchical integrated circuit design comprising a lower level block and an upper level block is obtained. The specification includes an initial routing plan for the lower level block. Subsequently, a compacted routing plan for the lower level block using constrained routing resources comprising fewer routing tracks than the initial routing plan and resulting in at least one unused track as well as a routing plan for the upper level block using the at least one unused track are generated.