Compact SRAM Cell Design with GAA Transistors for High-Speed Memory
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Solution Overview
Problem
Existing memory devices, particularly those with SRAM cells, face challenges in achieving optimal performance for high-speed and high-density applications due to limitations in design and interconnection structures.
Innovation Solution
The implementation of a compact SRAM cell design with a width of four poly pitches, utilizing gate-all-around (GAA) transistors, and optimized interconnection structures to reduce resistance and enhance performance for specific applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If existing memory devices are used for multiple applications, then versatility is improved, but performance optimization for specific applications deteriorates
Solution Approach 1:
The memory device is divided into multiple separate memory arrays, with each array dedicated to a specific application type (high-speed SRAM, high-density SRAM, embedded SRAM). This segmentation allows each array to be independently optimized for its intended application, resolving the contradiction between versatility and performance optimization by providing specialized structures for different uses while maintaining overall device adaptability through the multi-array configuration.
2Area of stationary object
If FinFETs and GAA transistors are used to reduce chip footprint, then area is reduced, but processing complexity increases
Solution Approach 1:
The patent transitions from planar transistor structures to three-dimensional FinFET and gate-all-around (GAA) transistor architectures. This dimensional change enables vertical stacking of transistor channels, dramatically reducing the horizontal chip footprint while the standardized fabrication processes for these 3D structures help manage processing complexity through established manufacturing techniques.
3Ease of manufacture
If standard interconnection structures are used, then manufacturing is simplified, but resistance and performance deteriorate
Solution Approach 1:
The interconnection structure implements local quality optimization by providing different interconnection configurations tailored to specific memory array types and application requirements. Rather than using a uniform interconnection structure throughout the device, the patent optimizes interconnection geometry, material, and layout locally for each memory array to minimize resistance and maximize performance while maintaining manufacturability through standardized process compatibility.
Data Source
AI summary
A memory device includes a first static random-access memory (SRAM) array having first SRAM cell groups arranged in an X-direction and a second SRAM array having second SRAM cell groups arranged in the X-direction. Each of the first SRAM cell groups includes two adjacent first SRAM cells arranged in the X-direction. Each of the first SRAM cells includes a first bit-line conductor and a first bit-line-bar conductor extending in a Y-direction. Each of the second SRAM cell groups includes two adjacent second SRAM cells arranged in the X-direction and sharing a second bit-line conductor and a second bit-line-bar conductor extending in the Y-direction. A first cell size of the first SRAM cells is larger than a second cell size of the second SRAM cells.