Compact Y-Junction for Submicron Silicon Waveguides
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Solution Overview
Problem
Existing Y-junctions in silicon photonic circuits suffer from high insertion loss, wavelength sensitivity, and fabrication challenges due to sharp corners violating CMOS design rules, leading to peeling off of photoresists, shallower etch, and voids in oxide cladding deposition, which degrade device performance and yield.
Innovation Solution
A submicron optical splitter device with a tapered section between input and output ports, optimized using FDTD and PSO algorithms, fabricated using 248 nm CMOS lithography, achieving a compact, low-loss, and wavelength-insensitive 1×2 power splitter with a minimum feature size of 200 nm.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If sharp corners are used in Y-junction design, then the device footprint is reduced and bending loss is minimized, but fabrication defects occur including peeling off of photoresists, shallower etch, and voids in oxide cladding deposition
Solution Approach 1:
The patent replaces sharp corners with circular arcs of optimized radius in the Y-junction design. This curvature modification eliminates fabrication defects associated with sharp corners while maintaining a compact footprint. The circular arc transition allows photoresist to adhere properly, enables uniform etch depth, and prevents void formation during oxide cladding deposition, thus resolving the contradiction between compact size and fabrication quality.
Solution Approach 2:
The patent optimizes the radius parameter of the circular arc to achieve the best balance between compact footprint and fabrication quality. By carefully selecting the arc radius within specific ranges, the design minimizes both device area and fabrication defects, demonstrating parameter optimization to resolve the technical contradiction.
2Manufacturing precision
If circular bends are used to avoid sharp corners, then fabrication quality is improved, but insertion loss increases to over 1 dB
Solution Approach 1:
The patent uses circular arc bends with optimized radius to achieve smooth light propagation while maintaining fabrication quality. The curvature is carefully selected to be large enough to avoid sharp corner defects but small enough to minimize bending loss and keep the device compact, thus resolving the contradiction between fabrication quality and insertion loss.
Solution Approach 2:
The patent transitions from a planar sharp-cornered Y-junction to a curved-path Y-junction using circular arcs. This dimensional change in the light propagation path allows smooth mode transformation and reduces scattering loss while maintaining the benefits of curved geometry for fabrication quality.
3Length of moving object
If submicron waveguide dimensions are used, then the advantage of high refractive index contrast is maximized for tight bends, but the minimum feature size rule of CMOS process is violated
Solution Approach 1:
The patent introduces circular arc bends with optimized radius in the submicron waveguide design. This curvature modification allows the use of tight bends enabled by high refractive index contrast while ensuring that all features, including the arc radius and waveguide width, remain above the CMOS minimum feature size rule, thus achieving both compact dimensions and CMOS compatibility.
Solution Approach 2:
The patent optimizes multiple parameters including waveguide width, bend radius, and Y-junction dimensions to ensure all features exceed the CMOS minimum feature size while still achieving submicron-scale compact design. This parameter optimization resolves the contradiction between small dimensions and manufacturing ease.
Data Source
AI summary
A compact, low-loss and wavelength insensitive Y-junction for submicron silicon waveguides. The design was performed using FDTD and particle swarm optimization (PSO). The device was fabricated in a 248 nm CMOS line. Measured average insertion loss is 0.28±0.02 dB across an 8-inch wafer. The device footprint is less than 1.2 μm×2 μm, orders of magnitude smaller than MMI and directional couplers.