Compacted ECC Blocks for Low-Power Memory Read Verification
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Solution Overview
Problem
Error correction coding (ECC) operations in computing systems lead to unnecessary power consumption and latency due to frequent error detection and correction checks, even when no errors are present in the data.
Innovation Solution
Data blocks and their corresponding ECCs are compacted using bitwise XOR operations, allowing for rapid determination of errors in the compacted data block, thereby reducing the need for individual ECC checks on each data block.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC checking is performed on every data block during read operations, then error detection capability is maintained, but power consumption increases significantly
Solution Approach 1:
Multiple data blocks are merged into a single compacted data block using XOR operations, and their corresponding ECCs are merged into a single compacted ECC. This allows a single ECC check on the compacted block to represent multiple original blocks, reducing the number of ECC operations from N per read to 1 per read, thereby significantly reducing power consumption while maintaining error detection capability.
Solution Approach 2:
The patent creates a compacted representation (copy) of multiple data blocks and their ECCs. By working with this compacted copy rather than the original multiple blocks, the system reduces the computational burden and power consumption of ECC operations while preserving the essential error detection functionality.
2Measurement precision
If individual ECC checks are performed on each data block, then error detection precision is maximized, but processing time and latency increase
Solution Approach 1:
Multiple data blocks and their ECCs are merged into single compacted versions using XOR operations. A single ECC check on the compacted block replaces N individual ECC checks on original blocks, reducing processing latency while maintaining error detection precision through the mathematical properties of XOR and ECC codes.
Solution Approach 2:
The compaction of multiple data blocks and their ECCs into compacted versions is performed as a preliminary action before ECC checking. This preprocessing step enables faster subsequent ECC verification by reducing the number of operations required, thereby reducing overall processing time without compromising error detection accuracy.
3Reliability
If ECC operations are performed on all data blocks during read, then data integrity is ensured, but system performance decreases due to redundant operations
Solution Approach 1:
The patent merges multiple data blocks into a single compacted block and their ECCs into a single compacted ECC. This allows the system to perform one ECC check instead of N checks per read operation, eliminating redundant operations and improving system performance while maintaining data integrity through the mathematical properties of the compaction and ECC verification process.
Solution Approach 2:
Instead of performing full ECC checks on every data block (excessive action), the patent performs a condensed ECC check on the compacted representation (partial action). This partial action is sufficient to detect errors in the original blocks due to the properties of XOR and ECC codes, thereby improving performance without sacrificing reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Significant power reduction of up to 75% is achieved by minimizing ECC checks on data blocks without errors, while maintaining error detection capability.
Implementation Method 1
Data blocks and their corresponding ECCs are compacted using bitwise XOR operations
Data Source
AI summary
In one embodiment, an apparatus comprises: a first circuit to compact a plurality of data blocks to a compacted data block and to compact a plurality of error correction codes (ECCs) associated with the plurality of data blocks to a compacted ECC; and a second circuit to generate a generated ECC for the compacted data block. The apparatus may directly send the plurality of data blocks to a destination circuit without error detection on the plurality of data blocks based at least in part on the compacted ECC and the generated ECC. Other embodiments are described and claimed.