Compacted L2P Table for Zoned Namespace Storage
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Solution Overview
Problem
Flash-based data storage devices face challenges in implementing higher-capacity storage due to the size constraints of the logical-to-physical (L2P) address translation table, which limits the random-access memory (RAM) available for other operations.
Innovation Solution
A Zoned Namespace data storage device employs a compacted L2P table with erase-block granularity, where the controller calculates the full physical address by combining the physical address of the erase block with additional components like word-line number, string-line number, page-type identifier, and page offset, reducing the overall size of the L2P table and optimizing RAM usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a traditional L2P table with page-level granularity is used, then accurate address translation is achieved, but the L2P table size becomes too large for constrained RAM
Solution Approach 1:
The patent segments the L2P table into two distinct tables: a compacted L2P table storing only erase block mappings at coarse granularity, and a detailed L2P table storing page-level mappings at fine granularity. This segmentation allows the system to maintain translation accuracy for individual pages while reducing overall memory consumption by leveraging the hierarchical structure where the compacted table provides erase block-level guidance and the detailed table provides precise page-level translation.
Solution Approach 2:
The patent introduces a hierarchical dimension to address translation by organizing mappings at multiple levels of granularity. The compacted L2P table operates at the erase block dimension (coarse), while the detailed L2P table operates at the page dimension (fine). This multi-dimensional approach allows the system to trade off between memory usage and translation precision systematically, using the compacted table for high-level navigation and the detailed table for precise address translation.
2Quantity of substance
If the L2P table size is reduced to fit in constrained RAM, then more RAM space is available for other operations, but the address translation becomes less efficient
Solution Approach 1:
The patent performs preliminary action by pre-compacting the L2P table to store only essential erase block mappings, thereby reducing the immediate memory footprint. This compacted structure serves as a preliminary guide that enables efficient address translation without requiring the full detailed mapping to be stored in RAM at all times, thus freeing up RAM space for other operations while maintaining translation efficiency through the hierarchical lookup process.
Solution Approach 2:
The patent introduces an intermediary structure in the form of the compacted L2P table that mediates between the host's logical address space and the physical erase block space. This intermediary provides a compressed representation of the mapping relationship, allowing the system to perform address translation efficiently without requiring the complete detailed mapping to reside in RAM, thus balancing memory consumption with translation performance.
3Quantity of substance
If a compacted L2P table with erase-block granularity is used, then RAM usage is optimized, but additional calculations are required to determine the full physical address
Solution Approach 1:
The patent segments the physical address into distinct components: the erase block address obtained from the compacted L2P table, and the offset within the erase block calculated from the logical address. This segmentation allows the system to retrieve the majority of the physical address information (erase block level) from the compacted table with minimal data, then compute only the necessary offset portion, thereby reducing overall memory usage while keeping the calculation complexity manageable through systematic address decomposition.
Solution Approach 2:
The patent changes the granularity parameter of the L2P table from page-level to erase block-level for the compacted table. This parameter change fundamentally alters the amount of data stored in the table, reducing RAM usage significantly. The trade-off is that the system must perform additional calculations to determine the precise page offset within the erase block, but this is acceptable given the substantial reduction in memory consumption and the systematic nature of the calculation based on the hierarchical address structure.
Data Source
AI summary
A Zoned Namespace data storage device configured to perform logical-to-physical (L2P) address translation using a compacted L2P having an erase-block granularity. For a host logical address, the compacted L2P table only has the physical address of the corresponding erase block, which provides a first part of the pertinent physical address. A controller of the data storage device calculates a second part of the pertinent physical address based on the superblock layout employed in the device and further based on the sequential write requirement to the superblocks. The controller then obtains the full physical address corresponding to the host logical address by combining the first and second parts. The erase-block granularity of the compacted L2P table enables the full L2P table of the device to have a relatively small size, which can beneficially be used to make more space available in the same amount of RAM for other operations.