Compacted Pipe Address Generation for Memory Controller Power Reduction
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Solution Overview
Problem
Current computer systems with non-uniform memory architecture (NUMA) face challenges in optimizing memory access performance due to the mapping of memory addresses, which leads to increased latency and constrained bandwidth when accessing data across computing nodes, limiting the flexibility and efficiency of memory allocation and usage.
Innovation Solution
The implementation of a system-on-a-chip (SoC) architecture with multiple memory controllers and programmable memory location configuration registers allows for the distribution of memory addresses across multiple memory devices, using hashing and binary decision trees to route memory requests efficiently and minimize latency, while also enabling flexible mapping and power management through memory folding and unfolding techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory addresses are mapped in large continuous sections to optimize local memory access, then local memory access performance is improved, but access latency to non-local memory increases and system flexibility is constrained
Solution Approach 1:
The memory address space is segmented and distributed across multiple memory controllers using interleave groups. Instead of mapping large continuous sections to single controllers, the system divides the address space into smaller interleaved segments that can be accessed by different controllers simultaneously, reducing the penalty for non-local access while maintaining local access performance.
Solution Approach 2:
The patent introduces a new dimension of memory organization by adding interleave group levels above traditional memory hierarchies. This creates a multi-dimensional address mapping structure where addresses are distributed not just across memory banks but across multiple controllers in an interleaved pattern, enabling parallel access paths and reducing latency without sacrificing local access speed.
2Speed
If memory addresses are mapped in large continuous sections, then local memory access is optimized, but bandwidth utilization across the system is limited
Solution Approach 1:
The memory system is segmented into multiple interleave groups, each managed by different memory controllers. This segmentation allows the system to utilize bandwidth from multiple controllers simultaneously by distributing memory requests across the segmented structure, thereby increasing overall bandwidth utilization while maintaining optimized local access within each segment.
Solution Approach 2:
The patent merges the capabilities of multiple memory controllers into a unified memory system through interleave group management. By combining the bandwidth resources of multiple controllers and coordinating their operation through the interleave structure, the system achieves higher aggregate bandwidth utilization while preserving the performance benefits of local memory access.
3Device complexity
If traditional memory mapping is used, then simplicity of memory allocation is maintained, but flexibility in memory allocation and power management is constrained
Solution Approach 1:
The patent implements dynamic memory allocation capabilities through configurable interleave group structures. The system can dynamically adjust memory mapping configurations, allocate memory to different interleave groups based on workload requirements, and modify allocation patterns without requiring complete remapping of the address space. This maintains relative simplicity while significantly increasing flexibility compared to traditional static mapping approaches.
Data Source
AI summary
In an embodiment, a system may support programmable hashing of address bits at a plurality of levels of granularity to map memory addresses to memory controllers and ultimately at least to memory devices. The hashing may be programmed to distribute pages of memory across the memory controllers, and consecutive blocks of the page may be mapped to physically distant memory controllers. In an embodiment, address bits may be dropped from each level of granularity, forming a compacted pipe address to save power within the memory controller. In an embodiment, a memory folding scheme may be employed to reduce the number of active memory devices and/or memory controllers in the system when the full complement of memory is not needed.