Companding ADC Architecture for Low-Power Picoamp Current Sensing
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Solution Overview
Problem
Existing analog to digital converters (ADCs) are highly consumptive of power, provide relatively low resolution, and are not suitable for applications with limited power budgets or requiring high performance.
Innovation Solution
The development of novel ADC designs and architectures that convert analog signals into high-resolution digital formats with reduced power consumption, including the use of non-linear N-bit digital to analog converters (DACs) and decimation filters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional ADC architectures are used, then power consumption is reduced, but resolution and performance are limited
Solution Approach 1:
The ADC is divided into multiple functional blocks including a non-linear N-bit DAC, decimation filters, and companding circuits. Each block performs a specific function in the conversion process, allowing high resolution to be achieved through coordinated operation of segmented components rather than a single power-hungry converter
Solution Approach 2:
The patent applies companding (compression-expansion) techniques that non-linearly transform the input signal range. By compressing the dynamic range before conversion and expanding it after, the system achieves higher effective resolution while using a lower-resolution physical DAC, thereby reducing power consumption
2Measurement precision
If high-resolution ADCs are implemented, then measurement precision improves, but device complexity increases
Solution Approach 1:
A non-linear N-bit DAC serves as an intermediary component between the digital control logic and the analog output. This intermediary, combined with companding circuits, enables high-resolution conversion while keeping the digital-to-analog conversion stage itself relatively simple and low-power
Solution Approach 2:
The patent replaces complex high-resolution direct conversion architectures with a combination of lower-resolution DAC, digital filtering, and analog companding. This substitution trades direct mechanical/electrical complexity for a more manageable multi-stage process using standard lower-resolution components
3Productivity
If conventional ADC designs are used, then device simplicity is maintained, but performance and resolution are insufficient
Solution Approach 1:
The ADC architecture dynamically switches between different conversion modes and utilizes time-varying companding functions. The decimation filters dynamically process sampled data at different rates, allowing the system to adapt its complexity to the specific performance requirements of each conversion task
Data Source
AI summary
An analog to digital converter (ADC) senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. The digital output signal provided to the N-bit DAC is an inverse function of the load current. The ADC is operative to sense very low currents (e.g., currents as low as is of pico-amps) and consume very little power (e.g., less than 2 μW).