Companion Chip Bus Bridge and FIFO for Microcontroller Data Consistency
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Solution Overview
Problem
Current microcontroller companion chips face challenges in efficiently mapping mandatory functions for engine management systems, particularly in speed detection and fuel injection control, due to limited bandwidth and the need for cost-effective hardware architectures that support advanced communication and signal processing.
Innovation Solution
A companion chip with a microprocessor bus domain and peripheral module bus domain connected via a bus bridge, incorporating a global time-management module, FIFO modules for data transmission, and a management module for ensuring data consistency through time and angle stamps, replacing the DMA component to manage ADC resources and schedule scanning inquiries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If more functionality is transferred to the companion chip to relieve the microcontroller, then the processing capability is improved, but the device complexity increases
Solution Approach 1:
The companion chip is divided into two separate bus domains: a microprocessor bus domain containing the microprocessor core, and a peripheral module bus domain containing communication and signal processing modules. These domains are connected via a bus bridge, allowing independent development and optimization of each domain while maintaining overall system functionality.
Solution Approach 2:
A bus bridge is introduced as an intermediary component between the microprocessor bus domain and the peripheral module bus domain. This mediator enables communication between the two domains while allowing them to operate independently, thus managing complexity through modular architecture.
2Productivity
If voluminous signal preprocessing is carried out in the chip to maximize interface bandwidth utilization, then the communication efficiency is improved, but the storage space requirement increases
Solution Approach 1:
The invention extracts and processes only the essential signal features in the companion chip through dedicated hardware modules for speed detection and fuel injection control. By taking out and processing only the critical data elements rather than retaining all raw data, the system achieves efficient preprocessing while minimizing storage requirements.
Solution Approach 2:
The system uses temporary FIFO buffers for data transmission between domains rather than permanent storage structures. These short-lived data structures hold data only during active transmission, allowing voluminous preprocessing without increasing permanent storage space requirements.
3Ease of manufacture
If a standardized microcontroller and companion chip partitioning is used, then the ease of manufacture is improved, but the adaptability to specific applications decreases
Solution Approach 1:
The companion chip is designed with mandatory modules for universal functions (communication with outside world, signal processing) that can be adapted to different applications. The microprocessor bus domain and peripheral module bus domain provide a universal architecture that can be configured for various engine management applications while maintaining ease of manufacture through standardized interfaces.
Data Source
AI summary
A companion chip for a microcontroller has a microprocessor bus domain and a peripheral module bus domain, which are connected to each other via a bus bridge. The microprocessor bus domain includes at least one microprocessor core, and the peripheral module bus domain includes at least one global time-management module as well as modules for communication with the outside world and for signal processing. The companion chip further includes at least one FIFO module for transmitting data within the chip, and between the chip and the microcontroller, and a management module connected to the FIFO module, which ensures the consistency of the data by associating a respective time value and/or an angle of rotation.