Comparator With Adaptive DFE for High-Speed ISI Compensation

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Solution Overview

Problem

High-speed serial communication systems face issues with inter-symbol interference (ISI) and attenuation, which are exacerbated by input gain stages, necessitating effective compensation methods.

Innovation Solution

A high-speed comparator utilizing a 14-tap decision feedback equalizer (DFE) with an unrolled first tap is implemented, which adapts to time-varying channel properties by using feedback of detected symbols to reduce ISI and maintain signal integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Illumination intensity

If input gain stages are used to increase signal amplitude, then signal amplitude is improved, but inter-symbol interference is amplified

Engineering Contradiction:
Improvesignal amplitudeVSAvoidinter-symbol interference
Core Design Contradiction:
Illumination intensityVSObject-generated harmful factors

Solution Approach 1:

The patent implements a decision feedback equalizer (DFE) that uses feedback of detected symbols to automatically adapt to time-varying properties of the communication channel. The DFE subtracts the estimated ISI from the incoming signal, effectively canceling the harmful interference while preserving the amplified signal amplitude.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The comparator circuit dynamically adjusts its decision threshold based on the detected signal characteristics and channel conditions. By changing the threshold parameter adaptively, the system maintains optimal detection performance despite the presence of amplified ISI and time-varying channel attenuation.

Inventive Principle:
Principle #35Parameter changes

2Object-generated harmful factors

If decision feedback equalizer is used to compensate inter-symbol interference, then inter-symbol interference is reduced, but device complexity increases

Engineering Contradiction:
Improveinter-symbol interferenceVSAvoidequalizer complexity
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The DFE is implemented with multiple taps (e.g., 14 taps) that process different time delays separately. Each tap handles a specific portion of the ISI, allowing the complex equalization function to be divided into manageable segments that can be implemented using standard circuit building blocks.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The DFE coefficients are made dynamically adjustable to adapt to time-varying channel conditions. This dynamic adaptation allows the equalizer to maintain effectiveness without requiring a complete redesign for different channel states, reducing the overall complexity compared to static high-order equalizers.

Inventive Principle:
Principle #15Dynamics

3Speed

If high-speed comparator is used to capture 26 Gbps input data, then data capture speed is improved, but eye opening precision requirements increase

Engineering Contradiction:
Improvedata capture speedVSAvoideye opening precision
Core Design Contradiction:
SpeedVSMeasurement precision

Solution Approach 1:

The DFE performs preliminary equalization of the incoming signal before it reaches the comparator. By pre-compensating for ISI and channel distortion, the signal presented to the comparator has improved eye opening, reducing the precision requirements for the high-speed comparison operation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The comparator uses an adaptive decision threshold as an intermediary reference level that adjusts based on signal conditions. This dynamic threshold acts as a mediator that compensates for residual distortions, allowing accurate decision-making at high speeds without requiring extremely precise fixed thresholding.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10389342B2Comparator
Publication Date: 2019.08.20 HEWLETT PACKARD ENTERPRISE DEV LP
  • US10389342B2 patent drawing
  • US10389342B2 patent drawing
  • US10389342B2 patent drawing

AI summary

A comparator includes a resolver controlled by a resolver clock signal and a differential amplifier controlled by a sampling clock signal. The resolver clock signal and the sampling clock signal are such that amplification at the differential amplifier during the reset phase of the resolver clock signal and the reset phase of the sampling clock signal begins during the resolving phase of the resolver.