Comparator System with Adjustable Rising and Falling Output Delays
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Solution Overview
Problem
Comparators used in high-performance portable devices face challenges in balancing fast response times with low power consumption, as faster comparators consume more power, and existing techniques do not effectively exploit asymmetries in rising and falling output delays to achieve power efficiency.
Innovation Solution
A comparator system with a controller that adjusts the rising and falling output delays based on specific requirements, allowing for asymmetrical operation modes to reduce power consumption while maintaining performance, by selectively enabling or disabling comparators and adjusting supply voltage or bias current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If faster comparators are used to reduce output delay, then response speed is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic adjustment of comparator output delays by controlling the switching timing of switches connected to capacitive loads. The controller modifies rising and falling output delays independently based on operational requirements, enabling the comparator to adapt its response characteristics dynamically rather than operating at a fixed speed, thus reducing power consumption while maintaining necessary performance
Solution Approach 2:
The patent changes the operational parameters of the comparator by adjusting the output delay times for rising and falling edges independently. By modifying these timing parameters according to specific operational modes (e.g., PFM vs PWM), the system optimizes the balance between response speed and power consumption without requiring a fundamentally different comparator design
2Device complexity
If symmetrical output delays are used, then design simplicity is maintained, but power efficiency is compromised
Solution Approach 1:
The patent explicitly implements asymmetrical output delays by independently controlling the rising output delay and falling output delay through separate switch networks and control logic. This asymmetry allows the system to optimize power consumption by having faster transitions when needed and slower transitions when acceptable, thereby improving overall power efficiency without significantly increasing design complexity
Solution Approach 2:
The system dynamically switches between symmetrical and asymmetrical delay modes depending on operational requirements. In some operating modes, symmetrical delays are used for simplicity, while in others, asymmetrical delays are implemented to maximize power efficiency, providing a flexible approach that balances design simplicity and power consumption
Data Source
AI summary
A comparator system and a method for comparing an input signal and a reference signal are presented. The system has a controller to adjust a rising output delay and/or a falling output delay of a system output signal. The system output signal is dependent on the comparison between the input signal and the reference signal. This system provides a more efficient comparator with reduced power consumption whilst still providing the required rising output delay and falling output delay for a given application. Techniques used in prior art will always resort to running the comparators at a speed that supports the speed requirements in the worst case conditions and does not exploit any asymmetries in the required rising output delay and falling output delay for a given application. When these asymmetries are exploited, further increases in power efficiency can be achieved.