Comparator Circuit With Adjustable Threshold and Hysteresis
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Solution Overview
Problem
Conventional comparators have a fixed threshold voltage close to zero and non-symmetrical hysteresis, making it difficult to achieve adjustable and well-controlled threshold and hysteresis without modifying transistor geometries, which results in variations with temperature and manufacturing changes.
Innovation Solution
A comparator design with dual differential input stages and adjustable reference voltages, where the switching threshold is determined by the difference between reference voltages, and hysteresis is controlled through feedback and digital-to-analog conversion, allowing for dynamic adjustment of threshold and hysteresis during operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional comparator design with fixed threshold close to zero is used, then circuit simplicity is maintained, but adaptability and precision control of threshold and hysteresis are limited
Solution Approach 1:
The comparator is divided into two differential input stages: a first stage for signal amplification and a second stage for threshold reference comparison. This segmentation allows independent control of signal processing and threshold setting, enabling adjustable threshold and hysteresis without significantly increasing overall circuit complexity.
Solution Approach 2:
The patent implements dynamic control of threshold and hysteresis parameters through digital-to-analog converters (DACs) that can programmably set reference voltages. This allows the comparator to adapt its characteristics during operation rather than being fixed at design stage, significantly improving versatility.
2Measurement precision
If transistor geometries are modified to achieve desired threshold and hysteresis, then threshold control is improved, but manufacturing precision and temperature stability deteriorate due to process variations
Solution Approach 1:
Instead of modifying physical transistor geometries to set threshold and hysteresis, the patent changes the electrical parameters by using programmable reference voltages from DACs. This allows precise digital control of threshold values without altering the physical transistor dimensions, thereby maintaining manufacturing precision and temperature stability.
Solution Approach 2:
The patent replaces the mechanical/geometric approach of setting thresholds through transistor geometry with an electrical/digital approach using DACs and reference voltages. This substitution enables precise threshold control through digital programming while avoiding the sensitivity to manufacturing variations and temperature changes inherent in geometric modifications.
3Adaptability or versatility
If additional circuitry is added to achieve adjustable threshold and hysteresis, then adaptability is improved, but device complexity increases
Solution Approach 1:
The second differential input stage serves multiple functions: it establishes the switching threshold through reference voltage comparison, controls hysteresis through feedback mechanisms, and provides temperature compensation. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby limiting the increase in overall device complexity while achieving high adaptability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables precise control of threshold and hysteresis, reducing the need for additional circuitry and allowing for adjustments 'on the fly', thereby improving the accuracy and reliability of comparator operations across various conditions.
Implementation Method 1
Transistor MN27 performs the function of providing positive feedback to introduce hysteresis into the comparator
Implementation Method 2
Transistor MN27 performs the function of providing positive feedback to introduce hysteresis into the comparator
Implementation Method 3
The drain of transistor MN2 is connected by conductor 2 to the gate and drain of P-channel current mirror input transistor MP10 and to the gate of P-channel current mirror output transistor MP9
Implementation Method 4
Inverters 7 and 8 provide additional gain to sharpen the edges of the comparator output signal
Data Source
AI summary
A comparator (12A,12B) includes a first differential input stage (10) including first (MN2) and second (MN3) input transistors and a load (MP9,MP10), the first input transistor (MN2) having a gate, source, and drain coupled to a first input voltage (Vin−), a first tail current source, and the load, respectively. The second input transistor has a gate and source coupled to a second input voltage (Vin+) and a first tail current source. A second differential input stage (11) includes a third (MN4) and fourth (MN5) input transistors, the third input transistor having a gate and source coupled to a first reference voltage (Vref+) and the second tail current source, respectively. The fourth input transistor (MN5) has a gate and a source coupled to a second reference voltage (Vref−) and the second tail current source, respectively. Drains of the third and fourth input transistors are coupled to the load. An output stage (6A) produces a comparator output voltage (Vout) in response to an output (V2) produced by the first and second (11) differential input stages. A switching threshold of the comparator is determined by a difference between the first and second reference voltages.