Comparator Array Offset Calibration With Shared Global Voltage Circuit
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Solution Overview
Problem
Existing comparator arrays in image sensors and computing-in-memory systems face challenges with high offset voltages, leading to reduced dynamic input range and performance, while traditional calibration methods either increase area and power consumption or compromise on calibration accuracy and time.
Innovation Solution
An offset calibration method and circuit for comparator arrays that utilize a global calibration voltage generation module, integrators, and local logic control circuits to achieve low area cost, short calibration time, and high calibration accuracy, allowing for a large calibration range and small calibration step.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If an independent calibration circuit is configured for each comparator to achieve high calibration accuracy, then calibration precision is improved, but circuit area and power consumption increase excessively
Solution Approach 1:
The patent merges multiple independent calibration circuits into a single shared calibration circuit that serves multiple comparators. The calibration circuit is configured to sequentially calibrate different comparators by receiving control signals and switching between comparators, thereby reducing the overall circuit area while maintaining calibration accuracy for each comparator.
Solution Approach 2:
The calibration circuit is designed with multi-functionality to calibrate multiple comparators using the same hardware resources. By incorporating switch elements and control logic, the single calibration circuit can be dynamically allocated to different comparators, achieving universal calibration capability across the comparator array without requiring dedicated circuits for each comparator.
2Reliability
If a larger-sized device is used to reduce offset voltage, then comparator performance is improved, but device area and load increase
Solution Approach 1:
The patent applies preliminary calibration action to comparators before they perform their main comparison function. By introducing a calibration phase that precedes the normal comparison operation, the system can correct offset voltages in advance using a small calibration circuit, thereby maintaining high comparator performance without requiring larger device dimensions.
3Measurement precision
If an additional calibration cycle is introduced before each comparison cycle to reduce offset voltage, then calibration accuracy is improved, but response speed decreases
Solution Approach 1:
The patent implements periodic calibration action where the calibration circuit operates at specific intervals rather than before every single comparison cycle. The calibration is performed periodically based on control signals, allowing the system to maintain acceptable offset calibration while reducing the frequency of calibration operations to preserve response speed for normal comparison tasks.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively reduces offset voltages, improves comparator performance, and minimizes area and power consumption, while maintaining high calibration accuracy and reducing mismatch between comparators.
Implementation Method 1
the integrators are configured to integrate the voltage generated by the global calibration voltage generation module in a calibration phase
Data Source
AI summary
Disclosed are an offset calibration method and circuit applied to a comparator array. The offset calibration circuit includes a global calibration voltage generation module, integrators, comparators, a global logic control circuit, and local logic control circuits; an entire comparator array shares the single global calibration voltage generation module, and each of the comparators only needs to introduce an integrator circuit, such that a large calibration range and a small calibration step are achieved, a long calibration cycle and a large circuit area are required, and the requirements for a low area are satisfied. The offset calibration method provided by the present disclosure is similar to a binary search algorithm, which is adopted to search for the offset voltage, the calibration step of12NVrefcan be realized by only N cycles, and short calibration time is thus realized.