Comparator Input Redundancy With Shared Backend for Offset Reduction
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Solution Overview
Problem
Conventional comparator systems with redundant comparators suffer from significant area overhead and diminishing returns in reducing offset voltage due to transistor mismatches, leading to inefficient use of resources.
Innovation Solution
The implementation of a comparator with backend circuitry and pairs of redundant input circuits, where each pair forms a differential pair of transistors, and a multiplexer system with control switches and transistors to select the best transistors for minimal offset, reducing the number of redundant comparators needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple redundant comparators are provided in parallel to reduce offset voltage, then the worst-case offset is reduced, but the area overhead increases significantly
Solution Approach 1:
The patent merges multiple comparator functions into a single comparator structure by providing redundant input circuits that share common backend circuitry. Instead of implementing multiple complete comparators in parallel, the invention combines multiple input circuit pairs (each with redundant transistors) that feed into shared backend circuitry, thereby reducing the total area while maintaining offset reduction capabilities
Solution Approach 2:
The backend circuitry serves multiple functions by processing signals from multiple redundant input circuit pairs. The multiplexer system allows the same backend circuitry to evaluate different transistor combinations and select the optimal one, making the backend circuitry universal rather than dedicated to a single comparator function
2Measurement precision
If many redundant comparators are used to achieve better offset performance, then the offset reduction improves, but the device complexity increases
Solution Approach 1:
The comparator is segmented into distinct functional blocks: multiple redundant input circuit pairs (each containing redundant transistors), multiplexer circuits for selection, and shared backend circuitry. This segmentation allows the complex function of offset reduction to be achieved through modular components working together, making the overall device complexity manageable despite the redundant elements
Solution Approach 2:
The invention introduces dynamic selection capability through multiplexers that can switch between different redundant input circuit pairs based on which combination provides the best offset performance. This dynamic aspect allows the system to adaptively select the optimal transistor configuration rather than being fixed, improving offset performance without proportionally increasing complexity
Data Source
AI summary
An apparatus is provided. The apparatus comprises backend circuitry and pairs of redundant input circuits. Each pair of redundant input circuits is configured to form a differential pair of transistors, and each redundant input circuit includes a multiplexer and a set of transistors. The multiplexer is coupled to the backend circuitry, and each transistor from the set of transistors has a first passive electrode, a second passive electrode, and a control electrode. The first passive electrode of each transistor from the set of transistors is coupled to the multiplexer, and the control electrodes from the set of transistors are coupled together.