Continuous-Time Comparator Bias Feedback for Lower PVT Power
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Solution Overview
Problem
Existing continuous-time comparators suffer from excessive power consumption due to a higher gain-bandwidth product than necessary, which is determined by worst-case process-voltage-temperature (PVT) corners, leading to inefficient operation under normal conditions.
Innovation Solution
A continuous-time comparator circuitry with a feedback mechanism that maintains a constant power supply voltage over amplifiers, using a current source and feedback sub-circuitry to stabilize the reference voltage, allowing for reduced power consumption and increased efficiency by minimizing current variation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the gain-bandwidth product is increased to achieve faster comparator speed, then the toggling speed improves, but the power consumption increases excessively
Solution Approach 1:
The patent implements dynamic biasing where the bias current is adjusted based on the operating conditions. The current mirror circuitry dynamically scales the bias current to match the actual signal amplitude and operating point, rather than using a fixed high current to cover worst-case scenarios. This allows the comparator to operate efficiently at lower currents under normal conditions while maintaining adequate performance margins.
Solution Approach 2:
The patent changes the bias current parameter dynamically based on operating conditions. By using current mirror circuitry that reflects the actual signal characteristics, the bias current is adapted to match real-world operating points rather than being fixed at worst-case levels. This parameter adaptation resolves the contradiction between speed and power consumption.
2Reliability
If the comparator is designed to meet worst-case PVT corner requirements, then the reliability under all operating conditions is ensured, but the power consumption becomes much higher than necessary for normal operation
Solution Approach 1:
The patent employs feedback mechanisms through current mirror circuitry that continuously monitors and adjusts the bias current based on actual operating conditions. This feedback allows the system to maintain reliable operation across PVT variations while consuming only the necessary power for current conditions, rather than constantly operating at worst-case power levels.
Solution Approach 2:
The comparator circuitry serves itself by using its own operating characteristics to determine the appropriate bias current level. The current mirror circuitry automatically adjusts the bias based on the actual signal amplitude and operating point, eliminating the need for external optimization or manual tuning for each operating condition.
3Speed
If two complementary differential pairs are provided in parallel with two current sources to double the bandwidth, then the speed performance improves, but the device complexity and power consumption increase
Solution Approach 1:
The patent makes the single differential pair and bias current circuitry serve multiple functions: it provides both the comparison function and dynamically adapts the bias to match operating conditions. This multi-functionality eliminates the need for separate parallel differential pairs while achieving efficient operation across the required bandwidth through intelligent bias management rather than brute-force parallelization.
Data Source
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AI summary
A continuous-time comparator circuitry (1, 5) for generating an output voltage signal (105) at an output node (15, 55) triggered by a difference between an input voltage signal (103) at an input node (13, 53) and a reference voltage signal (104) at a reference node (14, 54), the circuitry comprising: power supply nodes (11, 51, 12, 52); a current source sub-circuitry (170, 570); a feedback sub-circuitry (150, 550) configured to conduct a bias current between a second power supply node and a second intermediate node (121, 521); a first amplifier (130, 530) having as input the input node, as output the output node, and as voltage power supply first and second intermediate nodes; and a second amplifier (140, 540) having as input the reference node, as output a feedback node (16, 56), and as voltage power supply the first and second intermediate nodes; wherein the feedback node is fed back to the feedback sub-circuitry to provide a constant power supply voltage over the first and second amplifiers such that the triggering follows the reference voltage signal.