Comparator Circuit Biasing for Low-Kickback SAR ADCs
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Solution Overview
Problem
High-speed, low-power, and low-kickback noise comparators are needed for multi-comparator successive approximation analog-to-digital converters (ADCs) to improve precision and reduce power consumption, as traditional strong arm comparators suffer from significant kickback noise and inefficient reset and clocking processes.
Innovation Solution
An improved comparator circuit with a constant gate bias for the current source transistor and a pre-determinant phase to ramp drain nodes, reducing kickback noise and allowing for reduced power consumption without sacrificing performance, by keeping source and drain nodes at a stable voltage during reset and comparison states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional strong arm comparators are used in multi-comparator successive approximation ADCs, then comparison speed can be achieved, but significant kickback noise is generated and power consumption is high
Solution Approach 1:
The patent applies preliminary action by implementing a pre-determinant phase before the main comparison operation. During this phase, the drain nodes of the differential pair are ramped up to the supply voltage in advance, ensuring they are already at the correct voltage level when the comparison begins. This eliminates the need for voltage transitions during the comparison itself, thereby preventing kickback noise generation while maintaining fast comparison speed.
Solution Approach 2:
The patent applies equipotentiality by maintaining the drain nodes of the differential pair at a constant voltage level (supply voltage) throughout the comparison operation. By keeping these nodes at a stable potential through the pre-determinant phase and maintaining them there during comparison, voltage fluctuations are eliminated, which directly prevents kickback noise while preserving the ability to perform rapid comparisons.
2Power
If traditional strong arm comparators with reset and clocking processes are used, then comparison operation can be performed, but power consumption increases
Solution Approach 1:
The patent applies preliminary action by performing the voltage ramping of drain nodes in advance during the pre-determinant phase, before the actual comparison begins. This allows the main comparison operation to proceed without requiring additional power-intensive voltage transitions, thereby reducing overall power consumption while maintaining full comparison operation capability.
Solution Approach 2:
The patent applies continuity of useful action by maintaining the drain nodes at the supply voltage level throughout the comparison operation rather than allowing them to fluctuate. This continuous stable state eliminates the need for repeated power-intensive reset and recharging cycles, reducing power consumption while ensuring the comparator remains fully operational throughout the comparison process.
Data Source
AI summary
A comparator is described. The comparator includes a differential pair having first and second transistors to respectively receive first and second input signals. The comparator also includes a current sink or source transistor coupled to respective source nodes of the first and second transistors. The current sink or source transistor is coupled to receive a fixed bias to keep the current sink transistor active so that large voltage changes on the source nodes is avoided. The comparator circuit includes a latch circuit coupled to respective drain nodes of the first and second transistors. The latch circuit is to reach a final state to present the comparator's output signal. The comparator includes a first switch circuit coupled between the first transistor's drain node and the latch circuit, and a second switch circuit coupled between the second transistor's drain node and the latch circuit. The first and second switch circuits to allow the first and second transistors' respective drain node voltage and source node voltage to enter and exit the comparator's comparison state at a same voltage.