Comparator Circuitry With Non-Clocked Biasing for Low-Noise ADC Capture
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Solution Overview
Problem
Comparator circuitry in ADC systems faces challenges in achieving consistent performance under varying conditions, particularly in accurately comparing close voltage levels within tight time constraints, leading to noise and performance issues.
Innovation Solution
The implementation of a comparator circuitry that includes a biasing current source independent of the clock signal, with non-clocked transistors and cascode transistors, and noise-filtering capacitances, along with non-clocked gain-stage buffers and controllable resistances, to shield the comparator from clocked noise and improve noise performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clocked comparator circuitry is used to achieve fast conversion, then productivity is improved, but noise performance deteriorates due to clock feedthrough and data-dependent kickback
Solution Approach 1:
A non-clocked current source is introduced as an intermediary element to supply bias current to the differential pair. This non-clocked current source acts as a mediator between the clocked comparator circuit and the differential pair, isolating the differential pair from clock feedthrough while maintaining the fast conversion capability of the clocked comparator.
Solution Approach 2:
The comparator circuit is segmented into distinct functional blocks with different clocking strategies. The differential pair and current source are operated non-clocked to minimize noise, while the latch and other regenerative elements are clocked to enable fast conversion. This segmentation allows each block to be optimized for its specific function without compromising overall performance.
2Object-affected harmful factors
If non-clocked current source and shielding transistors are added to reduce noise, then noise performance is improved, but device complexity increases
Solution Approach 1:
The shielding function is merged with the existing transistor structure of the comparator. The transistors serving as shields are integrated into the differential pair configuration, where they simultaneously provide noise shielding and contribute to the differential amplification function. This merging avoids adding separate dedicated shielding components.
Solution Approach 2:
The non-clocked current source serves multiple functions: it provides bias current to the differential pair, acts as a noise shield, and enables the differential pair to operate independently of clock transitions. This multi-functionality reduces the need for separate dedicated components for each function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the noise performance and consistency of comparator circuitry, reducing thermal and flicker noise, data-dependent kickback, and clock feedthrough, while maintaining low power consumption and allowing for digital configuration.
Implementation Method 1
a biasing current source configured to provide a bias current which flows independently of the clock signal; a tail node connected to receive the bias current
Implementation Method 2
switching circuitry configured during each capture operation to control connections between the tail node and the first and second nodes based on the first and second comparator input signals such that said bias current is divided between said first and second paths in dependence upon the difference between magnitudes of the first and second comparator input signals
Implementation Method 3
noise-filtering capacitances, along with non-clocked gain-stage buffers and controllable resistances, to shield the comparator from clocked noise and improve noise performance
Implementation Method 4
The implementation of a comparator circuitry that includes a biasing current source independent of the clock signal, with non-clocked transistors and cascode transistors, and noise-filtering capacitances, along with non-clocked gain-stage buffers and controllable resistances, to shield the comparator from clocked noise and improve noise performance
Data Source
AI summary
In circuitry to capture differences between magnitudes of first and second comparator input signals in capture operations defined by a clock signal, first and second nodes are connectable to a tail node receiving a cock-signal-independent bias current along first and second paths. During each capture operation, switching circuitry controls connections between the tall node and the first and second nodes based on the input signals to divide the bias current between the first and second paths depending on the input signal magnitude difference. The switching circuitry comprises first and second transistors arranged such that conductivity of connections between the tail node and the first and second nodes Is controlled by the magnitudes of the input signals, and third and fourth non-clocked transistors controlled by a clock-signal independent gate bias signal.