Dynamic Comparator Boost Current Paths for Low-Voltage Latching
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Solution Overview
Problem
Dynamic comparators in analog-to-digital converters (ADCs) face challenges in latching speed due to semiconductor process variation, low supply voltage, and low temperature, while maintaining power efficiency.
Innovation Solution
A dynamic comparator design incorporating an amplifier circuit, latch circuit, reset circuit, boost circuit, and ready circuit, which includes a boost circuit to provide supplemental current paths during the active phase, enhancing latching speed without static current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a latching stage is added to generate full-scale output voltage, then the comparator provides complete output swing, but the latching speed becomes slow under semiconductor process variation, low supply voltage, and low temperature conditions
Solution Approach 1:
The patent applies preliminary action by pre-charging the latching node to a voltage level closer to the final output level before the latching operation begins. This reduces the voltage swing required during latching, thereby improving latching speed under slow conditions such as low supply voltage and low temperature, while still achieving the full-scale output voltage through the combined effect of the pre-charge and latching operations.
2Speed
If means for improving the speed of the latching stage are implemented, then latching speed increases, but static current consumption increases and power efficiency deteriorates
Solution Approach 1:
The patent implements periodic action by using a clock signal to periodically enable and disable the pre-charge transistor. During the active phase of the clock signal, the pre-charge transistor is enabled to charge the latching node, improving latching speed. During the inactive phase, the transistor is disabled to prevent static current consumption, thereby maintaining power efficiency while achieving speed improvement.
Data Source
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AI summary
A comparator is disclosed. The comparator includes an amplifier circuit, a latch circuit, and a boost circuit. The amplifier is configured to amplify a difference between the first and second differential inputs during an active phase of the comparator. The latch circuit includes first and second transistors, respectively coupled to first and second differential amplifier outputs, and configured to respectively drive first and second legs of the latch circuit during the active phase. The boost circuit includes first and second boost transistors respectively coupled to the first and second differential amplifier outputs, and configured to respectively provide a first supplemental current to the first differential output of the latch circuit and a second supplemental current to the second differential output of the latch circuit.