Comparator Buffer Circuit for Memory Cell Failing Current Detection
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Solution Overview
Problem
In semiconductor memory systems, comparing currents representing failing memory cells to a reference current is time-consuming due to increased electrical load as the number of memory cells increases, particularly in higher density memories, which slows down the programming process.
Innovation Solution
A circuit comprising a comparator coupled with a dynamic data cache array and a reference array, where a buffer circuit reduces parasitic load capacitances and resistances, allowing for faster sensing of failing memory cells by comparing the memory sense current to a reference current, with the ability to adjust the reference current to determine the number of failing memory cells within a specific range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells being evaluated during comparison increases, then the memory density increases, but the electrical load presented to the comparator increases and the comparison time increases
Solution Approach 1:
The patent segments the large number of memory cells into multiple groups, with each group evaluated by a dedicated comparator. This division reduces the electrical load on each individual comparator and shortens the comparison time for each group, while still enabling evaluation of the entire high-density memory array.
Solution Approach 2:
The patent introduces a spatial dimension by arranging comparators in a two-dimensional array configuration rather than using a single comparator. This multiplies the comparison capacity by adding parallel comparison paths, effectively reducing the time required to evaluate all memory cells in high-density memories.
2Quantity of substance
If the number of memory cells being evaluated during comparison increases, then the memory density increases, but the electrical load presented to the comparator increases
Solution Approach 1:
The patent segments the memory array into multiple groups, each handled by a separate comparator. This segmentation distributes the electrical load across multiple comparators rather than concentrating it on a single device, preventing overload and maintaining signal integrity in high-density configurations.
Solution Approach 2:
The patent introduces buffer circuits as intermediary elements between the memory cells and comparators. These buffers isolate and reduce the electrical load on the comparators, acting as mediators that protect the comparison circuitry from the harmful effects of high electrical load while enabling evaluation of large numbers of memory cells.
3Quantity of substance
If the comparison time increases, then the number of memory cells that can be evaluated increases, but the overall operation speed decreases
Solution Approach 1:
The patent divides the memory evaluation task into multiple parallel segments, each processed simultaneously by dedicated comparators. This segmentation enables the system to evaluate a large total number of memory cells while maintaining high operation speed, as multiple comparisons occur concurrently rather than sequentially.
Solution Approach 2:
The patent implements a dynamic architecture where multiple comparators can be selectively activated based on the evaluation needs. This dynamic configuration allows the system to adaptively balance between evaluating more memory cells and maintaining operation speed, optimizing performance for different memory densities and evaluation requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces the overall time required for repetitive comparisons, enabling quicker determination of the number of failing memory cells and improving the speed of the programming process by minimizing electrical loading on the comparator nodes.
Implementation Method 1
A buffer circuit reduces parasitic load capacitances and resistances
Data Source
AI summary
Apparatuses and methods for comparing a sense current representative of a number of failing memory cells of a group of memory cells and a reference current representative of a reference number of failing memory cells is provided. One such apparatus includes a comparator configured to receive the sense current and to receive the reference current. The comparator includes a sense current buffer configured to buffer the sense current and the comparator is further configured to provide an output signal having a logic level indicative of a result of the comparison.