Comparator Calibration Using Resistor Ladder Tap Adjustment
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Solution Overview
Problem
Comparator offsets, particularly dynamic offsets, in metal oxide semiconductor devices like switched comparator circuits, pose accuracy limitations due to random device mismatches and parasitic capacitances, which existing compensation techniques fail to adequately address, especially in small, low-power applications.
Innovation Solution
A method involving the calibration of comparator inputs by adjusting resistor ladder taps to meet a threshold condition, where a signal is applied to one input and a nominal voltage to the other, with iterative adjustments until a predetermined logic level count is reached, effectively compensating for both static and dynamic offsets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If device size is increased to reduce comparator offsets, then offset reduction is achieved, but power consumption increases and device complexity increases
Solution Approach 1:
The patent applies preliminary action by performing offset calibration before the comparator is used in its intended application. The calibration process pre-determines the optimal tap point in the resistor ladder that compensates for offsets, allowing the comparator to operate accurately without requiring larger device size or increased power consumption during normal operation
Solution Approach 2:
The patent changes the parameter of tap point selection in the resistor ladder to compensate for comparator offsets. By adjusting which tap point is selected (changing the reference voltage level), the system can offset the effects of device mismatches and parasitic capacitances without physically changing the device size or power consumption characteristics
2Measurement precision
If device size is increased to reduce comparator offsets, then offset reduction is achieved, but device complexity increases
Solution Approach 1:
The calibration process is performed in advance to determine the optimal tap point, storing this information for use during normal operation. This preliminary action eliminates the need for complex real-time adjustment mechanisms or larger device structures, maintaining simplicity while achieving offset compensation
Solution Approach 2:
The patent introduces an intermediary calibration process that uses the resistor ladder tap points as a mediator to compensate for comparator offsets. This intermediary mechanism allows offset compensation without requiring direct changes to the comparator structure itself, maintaining device simplicity
3Measurement precision
If static offset compensation techniques are applied, then static offset is reduced, but dynamic offset remains unaddressed
Solution Approach 1:
The patent applies a universal calibration approach using resistor ladder tap point selection that addresses both static and dynamic offsets through a single mechanism. The same tap point selection process that compensates for DC offsets also compensates for dynamic offsets caused by parasitic capacitances, making the solution multi-functional rather than requiring separate compensation techniques
Data Source
AI summary
A method and a device for canceling an offset voltage in an output of a comparator circuit include applying a signal to a first input of the comparator as a function of an initial tap point in a resistor ladder. While the signal is applied to the first input, a nominal voltage is applied to a second input of the comparator, and then an output of the comparator is analyzed. The signal to the first input is changed in response to the analyzing, by accessing a different tap point in the resistor ladder.