Comparator With Correlated Double Sampling for High-Speed ADC
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Solution Overview
Problem
Current CMOS image sensors face limitations in achieving high frame rates due to the exponential increase in conversion time with resolution, necessitating the development of high-performance, high-speed analog-to-digital converters (ADCs) for high-resolution applications.
Innovation Solution
A comparator with a correlated double sampling (CDS) scheme that expands the number of steps using ramp signals with different slopes, reducing size and power consumption, and an operating method that includes multiple steps for efficient analog-to-digital conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single slope ADC is used for high-resolution conversion, then conversion precision is improved, but conversion time increases exponentially limiting frame rate
Solution Approach 1:
The ADC conversion process is divided into multiple steps (first step, second step, third step) with different ramp signal slopes. Coarse conversion is performed in earlier steps with steeper slopes, and fine conversion is performed in later steps with gentler slopes, allowing high resolution without exponentially increasing total conversion time.
Solution Approach 2:
The ramp signal slope is dynamically adjusted across different conversion steps. The first ramp signal has a first slope for coarse conversion, the second ramp signal has a second slope for intermediate conversion, and the third ramp signal has a third slope for fine conversion. This dynamic adaptation of slope enables efficient multi-resolution conversion.
2Productivity
If multiple ramp signals with different slopes are used for multi-step conversion, then conversion speed is improved, but device complexity increases
Solution Approach 1:
The CDS block is designed to perform multiple functions: it generates multiple ramp signals with different slopes, performs correlated double sampling to eliminate offset errors, and controls the switching between different ramp signals. This multi-functionality reduces the need for separate dedicated circuits for each function.
Solution Approach 2:
The patent combines the ramp signal generation, CDS processing, and multi-step conversion control into a single integrated comparator structure. The CDS block generates all ramp signals and the comparison block processes all conversion steps, merging what could be separate modules into one unified device.
3Productivity
If traditional multi-step ADC structures are implemented, then high frame rate is achieved, but area and power consumption increase
Solution Approach 1:
The CDS block serves multiple purposes: generating ramp signals for different conversion steps, performing offset cancellation through correlated double sampling, and controlling the conversion process. This eliminates the need for separate offset cancellation circuits and ramp signal generators, reducing overall device area.
Solution Approach 2:
The same CDS block and comparison infrastructure are reused across all conversion steps. Rather than implementing separate ADC circuits for each step, the system recycles the same hardware resources through time-multiplexed operation with different ramp signals, minimizing area requirements.
Data Source
AI summary
A comparator includes: a comparison block suitable for comparing a pixel signal and a plurality of ramp signals; a correlated double sampling (CDS) block operatively coupled among a first input terminal receiving a first ramp signal used for first and third steps, a third input terminal receiving the pixel signal, and a negative input terminal of the comparison block, and suitable for performing CDS; a switch coupled between a second input terminal receiving a second ramp signal used for a second step and a positive input terminal of the comparison block; a capacitor coupled between a ground terminal and the positive input terminal of the comparison block; an amplification block suitable for buffering a comparison signal outputted from the comparison block; and a feedback control unit suitable for generating a control signal for controlling the switch based on the buffered comparison signal.