Comparator Circuit Layout for CDS-Based Reset Noise Reduction
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Solution Overview
Problem
Current CMOS image sensors face challenges in achieving high-performance analog-digital conversion due to reset noise, which affects image quality, and require improved comparator circuits to effectively apply Correlated Double Sampling (CDS) techniques.
Innovation Solution
A comparator circuit is designed with specific transistor configurations and switching signals to adjust auto-zero levels and parasitic capacitance, enabling effective CDS operations and improved bandwidth control within the analog-digital conversion circuit of the image sensor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional comparator circuit is used in the analog-digital conversion circuit, then the circuit structure is simple, but reset noise affects image quality and the CDS technique cannot be effectively applied
Solution Approach 1:
The comparator circuit is segmented into multiple functional blocks including a first comparator for CDS operation, a second comparator for additional processing, and associated switching circuits. This segmentation allows each block to perform specific functions that collectively eliminate reset noise while maintaining manageable complexity through modular design
Solution Approach 2:
The circuit performs preliminary auto-zero calibration before the main conversion process by using switching signals to pre-condition the comparators and eliminate offset voltages. This preliminary action ensures that the comparators are properly biased and reset noise is minimized before actual pixel signal processing begins
2Measurement precision
If the comparator circuit uses fixed transistor configurations, then the design is straightforward, but bandwidth control is limited and performance cannot be optimized
Solution Approach 1:
The transistor configurations within the comparator circuit are made dynamic through switching signals that reconfigure the transistor connections during different operational phases. This allows the circuit to adapt its bandwidth and gain characteristics dynamically, optimizing performance for different signal conditions while maintaining a relatively simple base design
Solution Approach 2:
The circuit changes operational parameters such as transistor switching states and connection topologies based on the phase of operation (e.g., calibration phase vs. conversion phase). This parameter changing approach allows the same hardware to achieve different performance characteristics needed for high-precision conversion without requiring multiple dedicated circuits
3Reliability
If reset noise is not compensated, then the circuit operation is simple, but image quality deteriorates and CDS technique cannot be applied
Solution Approach 1:
The circuit converts the harmful reset noise into a beneficial calibration reference by capturing the reset level signal and using it as one input to the comparator. Through the CDS technique, the reset noise is subtracted from the pixel signal, transforming what would be interference into a useful reference for noise cancellation
Solution Approach 2:
The comparator circuit incorporates feedback mechanisms where the output of the comparison process feeds back to adjust subsequent operations. The CDS technique uses feedback by comparing the pixel signal against the previously captured reset signal, creating a closed-loop system that actively compensates for reset noise and improves image quality
Data Source
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AI summary
Provided are a comparator and an image sensor including the same. The comparator includes a first input transistor including a gate connected to a first input node, a second input transistor including a gate connected to a second input node, a first load transistor including a drain connected to the first input transistor, a second load transistor including a drain connected to the second input transistor, a first shift transistor including a drain connected to the first load transistor, a second shift transistor including a drain connected to the second load transistor, a first bottom switch connected to the first load transistor in parallel, a second bottom switch connected to the second load transistor in parallel, a first top switch connected to the first shift transistor in parallel, and a second top switch connected to the second shift transistor in parallel.