Comparator Circuitry for ADC Noise Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Comparator circuitry in ADC systems faces challenges in achieving fast, low-power, and low-noise performance while maintaining consistent operation over varying conditions, particularly in applications requiring precise voltage level comparisons.
Innovation Solution
The proposed comparator circuitry incorporates latch circuitry with parallel current paths and gain-stage circuitry featuring cross-coupled and diode-connected transistors, along with timing circuitry to control voltage levels and current flow, enabling accurate difference capture between input signals through current mirroring and gain-stage amplification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional comparator circuitry is used, then the basic comparison function is achieved, but the comparator suffers from kickback noise, input offsets, and metastability issues that degrade performance
Solution Approach 1:
The comparator is divided into distinct functional stages: a first gain stage for initial amplification, a second gain stage for further amplification, and a latch stage for final decision. This segmentation isolates different functions to reduce interference and improve overall reliability by preventing kickback noise from propagating through the entire circuit.
Solution Approach 2:
The patent introduces intermediate buffering and gain stages between the input and the final latch decision. These intermediary stages act as mediators that amplify the input differential before it reaches the latch, reducing the impact of input offsets and preventing direct kickback to the input nodes.
2Measurement precision
If the comparator is designed for high gain to improve resolution, then measurement precision increases, but the circuit complexity and susceptibility to noise increase
Solution Approach 1:
The total gain requirement is segmented across multiple stages rather than achieved in a single stage. The first gain stage provides initial amplification with moderate gain, the second gain stage provides additional amplification, and the latch stage provides the final decision. This segmentation achieves high overall gain while keeping each individual stage simpler and more manageable.
Solution Approach 2:
The patent transitions from a single-stage voltage-mode comparator to a multi-stage architecture that incorporates both voltage amplification and current-mode latching. This dimensional change in the circuit architecture allows achieving high precision through cascaded stages rather than relying on a single complex high-gain stage.
3Productivity
If the comparator operates faster to improve productivity, then conversion speed increases, but noise and metastability issues worsen
Solution Approach 1:
The first and second gain stages perform preliminary amplification of the input differential voltage before the latch stage makes its decision. By preparing the signal in advance with sufficient voltage swing, the latch stage can make its decision more quickly and reliably, reducing metastability issues even at high operating speeds.
Solution Approach 2:
The comparator is operated in a clocked periodic manner with defined phases: a reset phase where the latch is prepared, a comparison phase where the actual comparison occurs, and a hold phase where the output is stable. This periodic operation allows the circuit to settle properly during each phase, reducing noise and metastability while maintaining high conversion speed through efficient time utilization.
Data Source
Figure 1
Figure 2~3
Figure 4
AI summary
Comparator circuitry for use in a comparator to capture differences between magnitudes of a pair of comparator input signals in a series of capture operations defined by a reset signal, the circuitry comprising: latch circuitry (800), comprising a pair of latch input transistors (802, 804) which form corresponding parts of first and second current paths of the latch circuitry respectively, which current paths extend in parallel between high and low voltage sources, a pair of latch output nodes (314, 316) at corresponding positions along the first and second current paths of the latch circuitry respectively, and timing circuitry (326, 328, 806); and gain-stage circuitry (700), comprising a pair of cross-coupled gain-stage output transistors (710, 712) connected along respective first and second current paths of the gain-stage circuitry which extend in parallel between high and low voltage sources, and a pair of diode-connected gain-stage output transistors (714, 716) connected in parallel with the pair of cross-coupled gain-stage output transistors, respectively.