Image Sensor Comparator Clamp for Stable AD Conversion Timing

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Solution Overview

Problem

In solid-state image sensors, the comparator's drain voltage varies with the pixel signal when it coincides with the reference signal, leading to a shift in the comparison result inversion timing, resulting in errors and non-linearity in the digital signal obtained through AD conversion, which degrades image quality.

Innovation Solution

The introduction of an input-side clamp transistor helps suppress the decrease in drain voltage, preventing the stop of current supply and maintaining the ideal inversion timing of the comparison result.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the comparator shares a power supply with the pixel circuit to reduce power consumption, then power consumption is reduced, but the drain voltage of the pMOS transistor varies according to the pixel signal level, causing inversion timing errors and degrading image quality

Engineering Contradiction:
Improvepower consumptionVSAvoidinversion timing accuracy
Core Design Contradiction:
Use of energy by moving objectVSMeasurement precision

Solution Approach 1:

The power supply configuration is segmented into two independent parts: the pixel circuit maintains its shared power supply arrangement for low power consumption, while the comparator is provided with a separate power supply to ensure stable drain voltage and accurate inversion timing. This segmentation allows each circuit to operate under optimal power supply conditions without compromising the other.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The solution transitions from a single-dimension power supply approach (shared power supply for both pixel circuit and comparator) to a two-dimension approach by introducing an independent power supply dimension for the comparator. This dimensional change enables the comparator to maintain stable operating voltage independent of pixel signal variations, thereby eliminating inversion timing errors while the pixel circuit continues to benefit from shared power supply efficiency.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Device complexity

If the drain voltage is allowed to vary with pixel signal level, then the circuit operation is simple, but the comparison result inversion timing shifts from ideal timing, causing errors in AD conversion

Engineering Contradiction:
Improvecircuit operation simplicityVSAvoidAD conversion accuracy
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The power supply system is segmented to provide independent voltage control to the comparator, separating it from the pixel circuit's power supply. This segmentation allows the comparator to maintain a stable drain voltage independent of pixel signal variations, ensuring accurate inversion timing and AD conversion precision without complicating the overall circuit operation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The drain voltage of the comparator is changed from a variable parameter (that varies with pixel signal level) to a fixed parameter (maintained at a stable level through independent power supply). This parameter change ensures that the inversion timing remains consistent and accurate across all pixel signal levels, thereby improving AD conversion accuracy while maintaining circuit simplicity.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP3928432B1Imaging device and comparator
Publication Date: 2025.01.22 SONY SEMICON SOLUTIONS CORP
  • EP3928432B1 patent drawingFigure 1
  • EP3928432B1 patent drawingFigure 2A
  • EP3928432B1 patent drawingFigure 2B

AI summary

A solid-state image sensor includes: an input transistor configured to output, from a drain, a drain voltage according to an input voltage input to a source in a case where the input voltage substantially coincides with a predetermined reference voltage input to a gate; and an output transistor configured to output a signal indicating whether or not a difference between the input voltage input to a source and the drain voltage input to a gate exceeds a predetermined threshold voltage as a comparison result between the input voltage and the reference voltage.