Comparator DC-DC Converter Timing Control Using DSP Delay
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Solution Overview
Problem
Comparator type DC-DC converters using synchronous rectification face challenges in reducing size and cost while achieving accurate dead time, on-time, and minimum off-time due to the use of analog delay circuits, which are prone to production and temperature variations.
Innovation Solution
A comparator-type DC-DC converter is designed with a control unit that includes a DLL section and a delay section configured with a Digital Signal Processor (DSP), generating delay signals for dead time, on-time, and minimum off-time, improving accuracy without increasing size or cost by using a single DSP instead of multiple analog delay circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple analog delay circuits are used to provide dead time, on-time, and minimum off-time, then the required timing functions are achieved, but the device size and manufacturing cost increase
Solution Approach 1:
The patent combines multiple separate analog delay circuits (for dead time, on-time, and minimum off-time) into a single integrated control circuit that generates all timing signals. This merging eliminates the need for multiple independent RC circuits, thereby reducing device size and component count while maintaining the required timing functions through a unified control architecture.
Solution Approach 2:
The control circuit is designed to perform multiple timing functions simultaneously - generating dead time, on-time, and minimum off-time signals within a single integrated structure. This multi-functional approach allows one circuit to replace what would traditionally require three separate analog delay circuits, reducing overall complexity while achieving all necessary timing requirements.
2Device complexity
If analog delay circuits are used for timing control, then the circuit size is reduced compared to digital implementations, but manufacturing precision deteriorates due to production and temperature variations
Solution Approach 1:
The patent transitions from analog timing parameters (RC time constants subject to variation) to digital timing parameters (discrete clock cycles). By using a digital counter driven by a stable clock signal, the timing accuracy is determined by the clock frequency and counter values rather than by resistor and capacitor values, thereby eliminating sensitivity to production and temperature variations while maintaining compact circuit size.
3Speed
If a comparator method is used to stabilize output voltage, then the response characteristic for abrupt load current increase is improved, but erroneous operation may occur due to power source voltage variation
Solution Approach 1:
The patent introduces a minimum off-time mechanism that prevents the comparator from triggering an on-pulse immediately after an off-pulse. This preliminary timing constraint ensures that the power source voltage has stabilized before allowing another comparison cycle, thereby preventing erroneous operations due to voltage transient effects while preserving the fast response capability of the comparator method.
Data Source
AI summary
A DC-DC converter 1 is provided with a voltage conversion unit 100 and a control unit 200. The control unit 200 includes: a comparator 20 and a trigger signal generation section 30 which generate a trigger signal when an output voltage is reduced from a reference voltage after having received a minimum off-time signal, a DLL section 40 generating a reference delay signal, a delay section 50 generating delay signals which are delayed from the trigger signal by a predetermined amount, further delayed by an on-time, still further delayed by a second dead time, and yet still further delayed by a minimum off-time, respectively, according to the reference delay signal, and a timing control section 60 determining a start time point and an end time point of an on-pulse, a start time point and an end time point of an off-pulse and also generating a minimum off-time signal, according to these delay signals.