Comparator Circuit for Dynamic Dead-Time and Shoot-Through Control
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Solution Overview
Problem
Existing pulser circuits face challenges in minimizing shoot-through current between switching transistors while maintaining required propagation delays and rise/fall times, as existing solutions are difficult to control optimally.
Innovation Solution
A comparator circuit is introduced that generates a delay between the ON time of a NMOS switch and the OFF time of a PMOS switch by sensing gate and drain currents, ensuring the PMOS switch is completely OFF before the NMOS switch turns ON, using a gate voltage sensing circuit, current sensing circuit, and current comparator circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If dead-time is increased between switching transistors to minimize shoot-through current, then power consumption is reduced, but propagation delay and rise/fall times deteriorate
Solution Approach 1:
The patent implements dynamic dead-time adjustment based on operating conditions. The dead-time control circuit dynamically modifies the dead-time period according to the actual switching state and operational requirements, allowing optimal balance between minimizing shoot-through current and maintaining fast propagation delay. This dynamic adaptation resolves the contradiction by making the system flexible rather than fixed.
Solution Approach 2:
The patent changes the dead-time parameter adaptively based on circuit conditions. By monitoring switching transistor states and adjusting the dead-time duration accordingly, the system optimizes power consumption while maintaining required speed performance. The parameter is not fixed but varies to achieve optimal trade-off between energy loss and time delay.
2Loss of energy
If dead-time is increased between switching transistors to minimize shoot-through current, then power consumption is reduced, but rise and fall times deteriorate
Solution Approach 1:
The patent implements dynamic dead-time adjustment based on operating conditions. The dead-time control circuit dynamically modifies the dead-time period according to the actual switching state and operational requirements, allowing optimal balance between minimizing shoot-through current and maintaining fast rise/fall times. This dynamic adaptation resolves the contradiction by making the system flexible rather than fixed.
Solution Approach 2:
The patent changes the dead-time parameter adaptively based on circuit conditions. By monitoring switching transistor states and adjusting the dead-time duration accordingly, the system optimizes power consumption while maintaining required rise and fall time performance. The parameter is not fixed but varies to achieve optimal trade-off between energy loss and switching speed.
3Loss of energy
If external circuits or resistor values are adjusted to control dead-time, then shoot-through current is reduced, but device complexity and ease of manufacture worsen
Solution Approach 1:
The patent merges the dead-time control function into the existing gate driver circuit architecture. Rather than adding separate external delay circuits or complex resistor networks, the control logic is integrated within the driver itself, simplifying the overall system. The dead-time control circuit shares resources with the main switching control, reducing component count and complexity.
Solution Approach 2:
The patent implements self-service by having the gate driver circuit automatically generate and control its own dead-time without requiring external adjustment components. The circuit monitors its own switching state and autonomously adjusts the dead-time period, eliminating the need for external delay circuits or manual resistor adjustments. This self-controlling mechanism reduces device complexity while achieving shoot-through current minimization.
Data Source
AI summary
This document discloses a comparator that is configured to control dead-time between two or more switching transistors. In particular, it is disclosed that the comparator is configured to generate a suitable delay between the switching “OFF” of a transistor and the switching “ON” of another transistor so that the amount of shoot through current flowing between these two transistors are greatly minimized.