Comparator Circuit Delay Cancellation Through Calibration Stages
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Solution Overview
Problem
Existing comparison circuits suffer from inherent delays, leading to errors in comparison results due to the time it takes for the output signal to change in response to input signal changes.
Innovation Solution
A comparison circuit is designed with a control circuit, capacitors, and a transconductance amplifier circuit that operates in different stages: automatic zero calibration, measurement, and delay sampling, allowing for the storage and compensation of DC offset and delay voltage signals to counteract inherent delays, enabling earlier output of comparison results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If continuous improvement on structures and device parameters of the comparison circuit is made, then the comparison result can be output quickly and accurately, but an inherent delay (usually tens of nanoseconds) causes an error in the comparison result
Solution Approach 1:
The patent applies preliminary action by performing delay calibration before actual comparison measurements. The system pre-determines the inherent delay value through calibration measurements and stores this compensation value for use during subsequent comparison operations, thereby eliminating the adverse effect of inherent delay on measurement accuracy
Solution Approach 2:
The patent implements feedback by using the measured inherent delay information to adjust and compensate the comparison results. The system continuously monitors and measures the actual delay characteristics and uses this feedback to correct the comparison output, ensuring accurate results despite the presence of inherent delay
2Speed
If the comparison circuit is designed to output comparison results quickly, then the response speed is improved, but the inherent delay causes timing errors in the comparison result
Solution Approach 1:
The system performs preliminary delay calibration to determine the inherent delay value before conducting speed-critical comparison operations. This pre-characterization of the delay allows the system to maintain fast response while compensating for timing errors using the pre-measured delay information
Solution Approach 2:
The patent uses feedback mechanisms where the inherent delay information is continuously fed back to adjust the comparison timing and results, allowing the system to maintain high response speed while ensuring measurement accuracy through real-time delay compensation
Data Source
AI summary
Comparison circuit and delay cancellation method are provided. The circuit includes a control circuit, capacitors and a transconductance amplifier circuit, wherein the control unit is configured to receive an input signal and control the comparison circuit to be in different working stages; the capacitors are configured to store a DC offset voltage signal at an automatic zero calibration stage; store the input signal when the output signal is inverted at a measurement stage; and store an equivalent delay voltage signal at a delay sampling stage; the transconductance amplifier circuit is configured to store the DC offset voltage signal to the capacitors at the automatic zero calibration stage; compare voltage signals on positive and negative input terminals and generate an output signal at the measurement stage; and store the equivalent delay voltage signal to the capacitors at the delay sampling stage. An inherent delay of the comparison circuit may be cancelled.