Comparator Circuit With Dual Sampling for Low-Voltage DRAM Readout
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Solution Overview
Problem
Existing comparators in mobile devices are unable to meet the requirements for lower operating voltage and energy consumption, which is essential for extending battery life and improving performance in dynamic random access memory (DRAM) data reading and writing.
Innovation Solution
A comparator circuit design that includes multiple sampling and positive feedback mechanisms, utilizing differential signals and reference signals to accelerate signal differences, ensuring accurate comparison results while reducing power consumption and response time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If existing comparator designs are used, then device simplicity is maintained, but power consumption is high and response rate is slow
Solution Approach 1:
The comparator is divided into multiple independent sampling circuits (first sampling circuit, second sampling circuit) that can operate in different modes. Each sampling circuit processes signals independently during different time periods, allowing the system to achieve high-speed comparison through parallel processing while maintaining low power consumption by activating only necessary circuits at any given moment.
Solution Approach 2:
The comparator employs periodic sampling operations where the first and second sampling circuits are activated alternately based on control signals. This periodic action allows the system to maintain high response rates by continuously processing signals in time-multiplexed fashion while reducing average power consumption compared to continuously operating a single high-speed comparator.
2Speed
If existing comparator designs are used, then circuit structure is simple, but response time is slow
Solution Approach 1:
The first and second sampling circuits perform preliminary sampling of the input signal and reference signal before the final comparison operation. This preliminary action prepares the signals in advance, allowing the main comparison circuit to operate at full speed without being bottlenecked by signal preparation, thus reducing overall response time while keeping the main comparison circuit relatively simple.
Solution Approach 2:
The sampling circuits act as intermediary components between the input signals and the final comparison operation. These intermediaries process and condition the signals in advance, enabling the main comparator to work at optimal speed without requiring a complex high-speed design, thereby achieving fast response with moderate circuit complexity.
3Measurement precision
If higher operating voltage is used, then comparison accuracy is improved, but energy consumption increases
Solution Approach 1:
The comparator dynamically adjusts its operating characteristics by switching between different sampling circuits based on control signals. This dynamic operation allows the system to maintain high comparison accuracy through multiple sampling opportunities while reducing energy consumption by not continuously operating all circuits at maximum voltage, adapting the voltage and power usage to the actual comparison needs.
Data Source
AI summary
The present disclosure provides a comparator and a decision feedback equalization circuit. The comparator includes: a first sampling circuit configured to generate, under the control of a first control signal and a clock signal, first differential signals according to a signal to be compared and a first reference signal; a first positive feedback circuit configured to accelerate a difference between the first differential signals; a second sampling circuit configured to generate, under the control of a second control signal and the clock signal, second differential signals according to the signal to be compared and a second reference signal, where the first reference signal is larger than the second reference signal; a second positive feedback circuit configured to accelerate a difference between the second differential signals.