Time-Domain Comparator Circuit With Edge Feedback Delay
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Solution Overview
Problem
Existing time-domain comparators require an increased number of delay stages to achieve longer delay times, leading to larger layout areas and inefficiencies in power consumption due to the need to amplify input signals for comparison.
Innovation Solution
A comparator design that includes both falling and rising edge delay circuits in each delay unit, allowing for feedback of delayed edges to reduce the number of stages required while maintaining delay time, utilizing primary and secondary conductivity type transistors to control delay times and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If the number of delay stages is increased to increase delay time, then the delay time is improved, but the layout area increases
Solution Approach 1:
The patent implements feedback by connecting the output of each delay stage back to its input, creating a closed-loop structure. This allows a single delay stage to be traversed multiple times, effectively multiplying the delay time without adding more stages. The feedback mechanism enables the signal to circulate through the same delay element repeatedly, achieving cumulative delay effect with minimal hardware.
Solution Approach 2:
The patent makes a single delay stage serve multiple functions by using it repeatedly through feedback. Instead of requiring separate delay stages for each time unit, one delay stage performs the delay function multiple times in sequence. This multi-functional usage reduces the total number of delay stages needed, thereby reducing layout area while maintaining or increasing total delay time.
2Duration of action of moving object
If the number of delay stages is increased to increase delay time, then the delay time is improved, but the device complexity increases
Solution Approach 1:
The feedback connection allows the output of a delay stage to be fed back to its input, creating a recursive structure. This enables the system to achieve extended delay time without proportionally increasing the number of stages. The feedback mechanism transforms a simple linear delay chain into a more efficient cyclic structure, reducing device complexity.
Solution Approach 2:
The patent merges multiple delay operations into a single delay stage by using feedback. Instead of having separate delay stages for each time unit, the same delay stage is reused multiple times through the feedback loop. This consolidation reduces the number of components and simplifies the overall device structure.
3Device complexity
If only one edge of the clock signal is delayed, then the circuit is simpler, but the number of stages must be increased to increase delay time
Solution Approach 1:
The feedback mechanism allows the delayed clock edge to be fed back and delayed again in subsequent cycles. This enables a single delay stage to accumulate delay effect over multiple cycles, achieving extended delay time without increasing circuit complexity. The feedback loop transforms a simple single-edge delay circuit into an efficient time-multiplexed delay system.
Solution Approach 2:
The patent utilizes periodic action by allowing the delay operation to repeat in each clock cycle. The delayed edge is fed back and processed again in the next cycle, creating a periodic delay pattern. This time-multiplexed approach enables cumulative delay effect without requiring multiple simultaneous delay stages, maintaining circuit simplicity while achieving extended delay time.
Data Source
AI summary
A comparator includes a first voltage-time conversion circuit, a second voltage-time conversion circuit, and a determination circuit. A first delay unit includes a first falling edge delay circuit that delays a falling edge based on a first input signal, a first rising edge delay circuit that delays a rising edge based on a second input signal, and a first output circuit. A second delay unit includes a second falling edge delay circuit that delays a falling edge based on the second input signal, a second rising edge delay circuit that delays a rising edge based on the first input signal, and a second output circuit.