Regenerative Comparator Fast Path for Low-Delay, Low-Power Latching
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Solution Overview
Problem
Traditional regenerative comparators face limitations in high-speed converters due to significant transmission delay, which is exacerbated by small input signals, and increased power consumption when attempting to reduce delay times.
Innovation Solution
A high-speed regenerative comparator circuit design incorporating a signal input stage, latch, current source, fast path, and reset switches controlled by clock signals to manage bias voltage and feedback networks, allowing for reduced transmission delay and controlled power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the current source is increased to reduce latching delay, then the transmission delay is reduced, but the power consumption increases
Solution Approach 1:
The patent applies dynamic current control by switching between different current source values based on operational phase. During the latch phase, a larger current is provided to reduce latching delay, while during other phases, the current is reduced to minimize power consumption. This is achieved through clock signal control of the current source circuit.
Solution Approach 2:
The patent implements periodic switching of the current source using clock signals. The current source is activated with higher current only during specific time windows when the latch needs to operate, and remains inactive or operates at lower current during other periods, thereby reducing overall power consumption while maintaining fast latching when needed.
2Loss of time
If the latch time constant is reduced to improve speed, then the transmission delay is reduced, but the power consumption increases
Solution Approach 1:
The patent dynamically adjusts the latch time constant by controlling the current through the latch circuit with clock signals. The time constant is reduced (by increasing current) only during the brief period when latching is required, and is increased (by reducing current) during other periods, achieving fast latching without continuous high power consumption.
3Loss of time
If the pre-latching delay is reduced to improve overall speed, then the transmission delay is reduced, but the circuit complexity increases
Solution Approach 1:
The patent merges the pre-latching delay reduction function with the existing latch circuit by using the same clock-controlled current source to serve both the signal input stage and the latch. This integration reduces pre-latching delay without adding separate complex circuitry, as the current control mechanism serves multiple purposes.
4Loss of time
If the input signal amplitude is increased to reduce delay, then the transmission delay is reduced, but the input signal range is limited
Solution Approach 1:
The patent changes the parameter being controlled from input signal amplitude to current source magnitude. By adjusting the current through the latch and signal input stage with clock signals, the circuit achieves reduced delay for small input signals without requiring large signal amplitudes, thereby maintaining adaptability to various input signal ranges while improving speed.
Data Source
AI summary
The present disclosure provides a high-speed regenerative comparator circuit, including: a signal input stage connected with an input terminal for differential signal input; a latch for caching and serving as a differential signal output terminal; a current source connected with the signal input stage for providing a power supply voltage; a fast path connected with the output terminal and used for increasing a voltage difference of the output terminal and turning on a positive feedback network of the latch; and a reset switch, including a first reset switch and a second reset switch. In the high-speed regenerative comparator circuit of the present disclosure, the transmission delay of the regenerative comparator circuit can be greatly reduced; and in a latch phase, a bias voltage is disconnected by means of timing control, and thus the power consumption of a comparator can be reduced. The present disclosure has simple circuit and high reliability.