Comparator Output Gating for Lower-Power PWM-ADC Sampling

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Solution Overview

Problem

High-frequency triggering of comparators in Pulse Width Modulated Analog to Digital Converters (PWM-ADCs) results in significant power dissipation, as the comparators are constantly enabled despite minimal changes in input signals, leading to inefficient energy usage.

Innovation Solution

Implementing a method to analyze the output of the comparator for transitions and operational states, allowing the comparator to be selectively operated in enabled, disabled, or low power states based on detected transitions, thereby controlling power supply and gating the quantization clock to reduce unnecessary triggering.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the comparator is triggered at high frequencies to yield an over sampled PWM signal, then the performance of the PWM-ADC is improved, but the power dissipation in the comparator increases considerably

Engineering Contradiction:

ImprovePWM signal sampling accuracyVSAvoidpower dissipation

Core Design Contradiction:

Measurement precisionVSLoss of energy

Solution Approach 1:

The comparator is enabled periodically based on the quantization clock signal rather than continuously. The control logic gates the quantization clock to enable the comparator only during specific time intervals when sampling is required, converting continuous operation into periodic operation to reduce power consumption while maintaining oversampled PWM signal quality

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The operational state of the comparator is dynamically changed between enabled and disabled states based on real-time analysis of the output signal. The control logic monitors the PWM signal and adjusts the comparator's enable state accordingly, allowing the system to adapt between high-performance mode (enabled) and low-power mode (disabled)

Inventive Principle:

Principle #15Dynamics

2Speed

If the comparator is constantly enabled to maintain readiness, then the response time is reduced, but the power consumption increases significantly

Engineering Contradiction:

Improvecomparator response timeVSAvoidenergy consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The control logic analyzes the output signal in advance to predict when transitions are likely to occur and proactively enables the comparator before these transitions happen. This preliminary enabling ensures the comparator is ready to detect transitions quickly while avoiding continuous operation, as it is only enabled when anticipated to be needed

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system implements feedback by continuously analyzing the comparator's output signal to detect transitions. Based on this feedback, the control logic adjusts the enable state of the comparator, creating a closed-loop control system that optimizes power consumption while maintaining accurate transition detection

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS7570190B1Method and system for operating a comparator

Publication Date: 2009.08.04 MOTOROLA SOLUTIONS INC

AI summary

A method and system for operating a comparator (602) is provided. The method includes analyzing an output (612) of the comparator (602) based on one or more of a transition of the output, present operational state of the comparator, and at least one time instant corresponding to the output. The method further includes controlling an operational state of the comparator (602) based on the analysis of the output (612).