Comparator Hysteresis Circuit for Low Dynamic Power
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Solution Overview
Problem
Comparators face challenges in minimizing power consumption, particularly when input signals are close to triggering, leading to unnecessary power consumption due to small voltage fluctuations, which is problematic in ultra-low power applications like DC-DC converters.
Innovation Solution
A comparator design incorporating positive and negative input terminals, biasing current sources, amplification circuits with hysteresis, current mirroring circuits, current-controlled driver circuits, a latch circuit with CMOS transistors, and a current starved inverter to limit shoot-through current, optimizing power consumption by employing internal hysteresis and mirroring ratios to manage slow input transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a comparator operates with high gain to detect small voltage differences, then measurement precision is improved, but power consumption increases due to continuous operation near triggering
Solution Approach 1:
The comparator uses hysteresis to create periodic-like switching behavior where the output remains stable in one state until the input difference exceeds a threshold, then switches and remains stable until the opposite threshold is reached. This periodic switching action reduces continuous power consumption while maintaining detection capability.
Solution Approach 2:
The load circuit provides positive feedback to the amplification circuit to enable hysteresis, where the output state feeds back to influence the input threshold. This feedback mechanism creates stable operating regions that reduce power consumption by preventing continuous switching near the triggering point.
2Measurement precision
If the comparator uses high gain amplification to detect small signal differences, then measurement precision is improved, but speed decreases due to longer settling time
Solution Approach 1:
The comparator dynamically adjusts its operating characteristics through hysteresis, where the effective threshold changes based on the current output state. This dynamic behavior allows the circuit to quickly transition between states while maintaining high precision detection, resolving the trade-off between speed and precision.
3Reliability
If the comparator operates continuously to maintain readiness for signal comparison, then reliability is improved, but power consumption increases
Solution Approach 1:
The comparator enters low-power states during stable operation and only activates fully when triggered by significant input changes. The hysteresis mechanism ensures that once triggered, the comparator remains active long enough to complete the comparison and establish a stable output, then returns to low-power mode, creating periodic active-low-power cycles that improve reliability while reducing average power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves low dynamic power consumption even with slow input slew rates without compromising speed or output rise time, making it suitable for ultra-low power applications.
Implementation Method 1
a load circuit configured to provide positive feedback for the amplification circuit to enable hysteresis
Implementation Method 2
an output circuit implementing a current starved inverter for limiting a shoot-through current from a positive voltage supply to a negative voltage supply
Data Source
AI summary
According to an aspect, there is provided a comparator comprising input terminals, first, second and third biasing current sources configured to output first, second and third biasing currents, an input circuit driven by the first biasing current source and comprising an amplification circuit and a load circuit configured to provide positive feedback for the amplification circuit, first and second current mirroring circuits for forming, with the input circuit, first and second current mirrors producing first and second current mode signals, first and second current-controlled driver circuits configured to be controlled by the second and third biasing currents, respectively, and the first and second current mode signals, respectively, a latch circuit comprising first and second cross-coupled complementary metal-oxide semiconductor transistors acting as a latch having substantially rail-to-rail output voltage swing and being driven, respectively, by the first and second current-controlled driver circuits and an output circuit implementing a current starved inverter.