Comparator Hysteresis Circuit With Feedback-Stabilized Thresholds

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Solution Overview

Problem

Conventional comparator circuits with hysteresis function suffer from hysteresis window drift due to variations in semiconductor manufacturing processes and temperature, leading to output errors and instability.

Innovation Solution

A comparator circuit design incorporating two NMOS transistors, two PMOS transistors, and resistors to stabilize the hysteresis window, where the PMOS transistors' threshold voltage is compensated through a feedback circuit and resistor configuration, reducing temperature sensitivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If two PMOS transistors are added to form a hysteresis comparator circuit, then output oscillation caused by input noise is avoided, but the hysteresis window changes due to manufacturing process or temperature variations

Engineering Contradiction:
Improveoutput stabilityVSAvoidhysteresis window stability
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent introduces a feedback circuit that senses the threshold voltage of the PMOS transistors and adjusts the hysteresis window dynamically to compensate for threshold voltage variations. This feedback mechanism ensures that the hysteresis window remains stable despite manufacturing process or temperature changes, while maintaining the noise rejection capability provided by the hysteresis function.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent employs parameter changes by adjusting the hysteresis window parameters based on the threshold voltage of the PMOS transistors. Through dynamic parameter adjustment, the circuit compensates for threshold voltage drift caused by manufacturing variations or temperature changes, thereby stabilizing the hysteresis window while preserving the noise immunity provided by the hysteresis function.

Inventive Principle:
Principle #35Parameter changes

2Object-affected harmful factors

If PMOS transistors are used to set threshold values for hysteresis, then noise-induced output errors are eliminated, but temperature sensitivity of the hysteresis window increases

Engineering Contradiction:
Improvenoise immunityVSAvoidtemperature sensitivity
Core Design Contradiction:
Object-affected harmful factorsVSTemperature

Solution Approach 1:

The feedback circuit monitors the threshold voltage of the PMOS transistors and dynamically adjusts the hysteresis window to compensate for temperature-induced threshold voltage changes. This maintains noise immunity while reducing temperature sensitivity of the hysteresis window.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The circuit performs self-compensation by using the threshold voltage information from the PMOS transistors to automatically adjust the hysteresis window parameters, eliminating the need for external temperature compensation mechanisms while maintaining noise rejection capability.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10763840B1Comparator circuit with hysteresis function and a semiconductor device thereof
Publication Date: 2020.09.01 LITE ON SINGAPORE PTE LTD
  • US10763840B1 patent drawing
  • US10763840B1 patent drawing
  • US10763840B1 patent drawing

AI summary

A comparator circuit includes a first comparator, a second comparator and an inverter. The first comparator includes two N-channel metal-oxide-semiconductor (NMOS) transistors, two first P-channel metal-oxide-semiconductor (PMOS) transistors and two second PMOS transistors. A gate of the NMOS transistors respectively receives first and second voltages, and sources of the first PMOS transistors are connected to first and second resistors, respectively. The first comparator outputs differential output signals from drains of the NMOS transistors according to the voltage difference between the first and second voltages. An output of the second comparator is connected to gates of the first PMOS transistors of the first comparator. An input of the inverter is connected to the output of the second comparator, and an output of the inverter is connected to gates of the PMOS transistors.