Imaging Comparator Input Hold During FD Boosting

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Solution Overview

Problem

The interruption of the signal line during the boosting period of the floating diffusion (FD) in imaging devices leads to a voltage drop in the comparator, potentially increasing the settling time and decreasing the frame rate.

Innovation Solution

An imaging device with a correction circuit that holds the potential of the non-inverting input terminal of the comparator at the pre-boosting level during the boosting period, using transistors and switches to maintain the voltage stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the signal line is interrupted during the boosting period of the floating diffusion, then charge transfer efficiency is improved, but the frame rate decreases due to increased settling time

Engineering Contradiction:
Improvecharge transfer efficiencyVSAvoidframe rate
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The correction circuit performs preliminary action by holding the potential of the non-inverting input terminal at the pre-boosting level during the boosting period. This is achieved by switching the first switch to the off-state and the second switch to the on-state before the boosting period begins, thereby preparing the comparator input in advance to prevent voltage drop and reduce settling time, resolving the contradiction between charge transfer efficiency and frame rate.

Inventive Principle:
Principle #10Preliminary action

2Object-affected harmful factors

If the signal line is interrupted during the boosting period, then black floating (flare) is avoided, but voltage drop occurs in the comparator

Engineering Contradiction:
Improveblack floatingVSAvoidvoltage stability
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

The correction circuit acts as an intermediary between the selection transistor and the comparator's non-inverting input terminal. It uses a pair of transistors and switches to mediate the voltage signal, holding the potential at the pre-boosting level during the boosting period. This intermediary structure prevents the voltage drop from reaching the comparator while still allowing the boosting operation to proceed, thus avoiding black floating while maintaining voltage stability.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Manufacturing precision

If the signal line is interrupted during the boosting period, then charge transfer efficiency is improved, but settling time increases

Engineering Contradiction:
Improvecharge transfer efficiencyVSAvoidsettling time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The correction circuit performs preliminary action by pre-establishing the holding potential during the boosting period through the second transistor and second switch configuration. By switching to the holding configuration before boosting begins, the comparator input is prepared in advance, eliminating the need for extended settling time after the boosting period, thus resolving the time loss while maintaining improved charge transfer efficiency.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12284456B2Imaging device and distance measurement system
Publication Date: 2025.04.22 SONY SEMICON SOLUTIONS CORP
  • US12284456B2 patent drawing
  • US12284456B2 patent drawing
  • US12284456B2 patent drawing

AI summary

Provided is an imaging device capable of suppressing a decrease in a frame rate while improving charge transfer efficiency. An imaging device according to an embodiment of the present disclosure includes: a photoelectric conversion element; a signal converter that is boosted when charge transferred from the photoelectric conversion element is converted into a pixel signal; a selection transistor that interrupts a signal line of the pixel signal during a boosting period of the signal converter; a comparator including a non-inverting input terminal to which the pixel signal is input via the selection transistor, an inverting input terminal to which a ramp signal is input, and an output terminal which outputs a comparison result between the pixel signal and the ramp signal; and a correction circuit that holds a potential of the non-inverting input terminal in the boosting period at a potential of the non-inverting input terminal before the boosting period.