Comparator Input Stage Isolation for Low-Noise ADC Capture
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Solution Overview
Problem
Comparator circuits in ADC systems face challenges in achieving fast, low-power, and low-noise performance, particularly when dealing with close voltage levels, which affects the overall accuracy and efficiency of sub-ADC units and analogue-to-digital conversion.
Innovation Solution
The solution involves shielding the first and second transistors from clocked circuitry noise, using a non-clocked biasing current source and cascode transistors, and incorporating CMOS inverters and controllable resistances to improve noise performance and reduce data-dependent and clock kickback noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clocked circuitry is used to improve conversion speed, then productivity is improved, but noise is generated that degrades measurement precision
Solution Approach 1:
The comparator circuit is segmented into multiple stages: a first stage with transistors directly receiving input signals and biased by a non-clocked current source, and a second stage that is clocked. This segmentation isolates the sensitive input stage from clocked circuitry noise while maintaining fast conversion speed in the second stage.
Solution Approach 2:
A non-clocked biasing current source is introduced as an intermediary between the power supply and the first stage transistors. This intermediary provides stable biasing without introducing clock noise to the sensitive input stage, thereby improving noise performance while allowing the rest of the circuit to operate at high speed.
2Productivity
If biasing current is increased to improve conversion speed, then productivity is improved, but power consumption increases
Solution Approach 1:
The biasing current source is designed to dynamically adjust the biasing current based on operating conditions. During conversion operations, sufficient current is provided for fast switching, while during idle periods or low-precision modes, the current is reduced to minimize power consumption.
Solution Approach 2:
The biasing current parameter is made variable rather than fixed. The circuit can adjust the biasing current level to optimize the trade-off between conversion speed and power consumption depending on the specific application requirements and operating conditions.
3Measurement precision
If transistors are placed close to input signals to reduce noise, then measurement precision is improved, but susceptibility to clock kickback noise increases
Solution Approach 1:
The first stage transistors are extracted from the clocked circuitry environment and placed in a separate, noise-free zone that is directly biased by the non-clocked current source. This physical and electrical separation removes the transistors from the harmful clock kickback noise environment while maintaining their proximity to input signals for low noise performance.
Data Source
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AI summary
Comparator circuitry for use in a comparator to capture differences between magnitudes of first and second comparator input signals in a series of capture operations defined by a clock signal, the circuitry comprising: a biasing current source configured to provide a bias current which flows independently of the clock signal; a tail node connected to receive the bias current; first and second nodes conductively connectable to said tail node along respective first and second paths; and switching circuitry configured during each capture operation to control connections between the tail node and the first and second nodes based on the first and second comparator input signals such that said bias current is divided between said first and second paths in dependence upon the difference between magnitudes of the first and second comparator input signals, wherein: the switching circuitry comprises a first transistor whose channel forms part of the first path and a second transistor whose channel forms part of the second path; gate terminals of the first and second transistors are controlled by the first and second comparator input signals, respectively, such that the conductivity of the connections between the tail node and the first and second nodes is controlled by the magnitudes of the first and second comparator input signals; the switching circuitry further comprises a third transistor whose channel forms part of the first path and a fourth transistor whose channel forms part of the second path; the third and fourth transistors are located along their respective paths between the first and second transistors and the first and second nodes, respectively; and the third and fourth transistors are non-clocked transistors whose gate terminals are controlled by a gate bias signal which is also independent of the clock signal.