Comparator Kickback Compensation in CDAC-Based ADCs
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Solution Overview
Problem
Latched comparators in analog-to-digital converters (ADCs) experience noise-induced errors due to kickback noise when the output state changes, which can be exacerbated by capacitive digital-to-analog converters (CDACs), leading to reduced accuracy and increased power consumption.
Innovation Solution
The implementation of kickback compensation circuits, including edge rate control circuitry and bypass circuitry, which adjust the edge rate of the comparator's output signal based on bit significance and route kickback current away from the comparator inputs, respectively, to mitigate noise effects and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If latched comparator is used in ADC, then power consumption is reduced, but kickback noise increases causing measurement errors
Solution Approach 1:
A bypass circuit is introduced as an intermediary component that provides a dedicated path for kickback current to flow away from the comparator inputs. This mediator circuit allows the latched comparator to maintain its low power consumption while preventing kickback noise from degrading measurement precision.
Solution Approach 2:
The harmful kickback current is extracted from the main signal path by providing a separate bypass path. This separates the useful comparison function from the harmful kickback effect, allowing the comparator to operate in low-power mode while the bypass circuit handles the noise isolation.
2Productivity
If edge rate of comparator output is increased for higher significance bits, then conversion speed is improved, but kickback noise is exacerbated
Solution Approach 1:
The edge rate of the comparator output is made dynamic rather than fixed. The edge rate is adjusted based on the significance of the bit being converted - higher for more significant bits to maintain conversion speed, and lower for less significant bits to reduce kickback noise. This dynamic adaptation resolves the contradiction between speed and noise.
Solution Approach 2:
The edge rate parameter of the comparator output is changed adaptively during the conversion process. By modifying this parameter based on bit significance, the system achieves high conversion speed for critical bits while minimizing kickback noise for less critical bits.
3Measurement precision
If bypass circuit is added to route kickback current, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The bypass circuit serves as a relatively simple intermediary component that provides effective kickback current routing. While it does increase device complexity, the added complexity is minimal compared to the significant improvement in measurement precision, making it an acceptable trade-off.
Data Source
AI summary
An analog-to-digital converter (ADC) includes a comparator, a voltage reference circuit, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a plurality of capacitors. Each of the capacitors of the first CDAC includes a top plate coupled to a first input of the comparator, and a bottom plate switchably coupled to an output of the voltage reference circuit. The second CDAC includes a plurality of capacitors. Each of the capacitors of the second CDAC includes a top plate coupled to a second input of the comparator, and a bottom plate switchably coupled to a ground reference.