Capacitive Comparator Kickback Compensation in SAR ADCs
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Solution Overview
Problem
Latched comparators in analog-to-digital converters (ADCs) experience kickback noise during state changes, which introduces errors due to large signal swings, especially when driven by capacitive sources, leading to noise on inputs and outputs, and affecting comparison accuracy.
Innovation Solution
The implementation of kickback compensation circuits, including edge rate control and bypass circuitry, in successive approximation ADCs, which adjust the edge rate of comparator outputs based on bit significance and route kickback current away from comparator inputs, respectively, to mitigate noise and impedance mismatch issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If latched comparators are used in ADCs, then power consumption is reduced and output state is maintained, but kickback noise is generated during state changes affecting comparison accuracy
Solution Approach 1:
A bypass circuit is introduced as an intermediary component that provides an alternative current path during comparator state transitions. The bypass circuit includes a switch that connects a capacitor to ground, allowing kickback current to flow through the bypass path rather than through the capacitor inputs, thereby isolating the capacitor from harmful kickback effects while maintaining the low-power latched comparator operation
Solution Approach 2:
The kickback current, which is inherently harmful to comparison accuracy, is redirected through the bypass circuit to serve a useful function. By providing a dedicated current path that shunts kickback away from sensitive capacitor nodes, the harmful effect is converted into a controlled current flow that protects the comparison accuracy while maintaining the benefits of latched comparator operation
2Power
If capacitive sources drive the comparator, then the comparator can operate with low power, but impedance mismatch and noise are introduced during state changes
Solution Approach 1:
The bypass circuit acts as an intermediary between the comparator output and the capacitor inputs, providing a controlled current path that prevents direct coupling of kickback noise to the capacitor nodes. This intermediary structure allows the capacitive driver to maintain low-power operation while isolating the system from impedance mismatch and noise effects during state transitions
3Productivity
If edge rate of comparator output is increased for higher significance bits, then conversion speed is improved, but kickback noise magnitude increases
Solution Approach 1:
The bypass circuit provides a dedicated current path that mediates between the high-speed comparator output and the sensitive capacitor inputs. By controlling the timing and path of current flow during edge transitions, the bypass circuit enables faster edge rates for improved conversion speed while preventing the associated kickback noise from coupling into the capacitor nodes and degrading signal integrity
Data Source
AI summary
An analog-to-digital converter (ADC) includes a comparator, a voltage reference circuit, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a plurality of capacitors. Each of the capacitors of the first CDAC includes a top plate coupled to a first input of the comparator, and a bottom plate switchably coupled to an output of the voltage reference circuit. The second CDAC includes a plurality of capacitors. Each of the capacitors of the second CDAC includes a top plate coupled to a second input of the comparator, and a bottom plate switchably coupled to a ground reference.