Differential Comparator Latch Layout for Low Offset Voltage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing comparator circuits suffer from significant offset voltage due to process variations and mismatches, particularly in dynamic cross-coupled inverter latches, which complicates manufacturing and increases costs.
Innovation Solution
A differential comparator design with two pairs of latch transistors and input transistors, where the gates of latch transistors on one current path are coupled to the output terminal between latch transistors on the other path, and input transistors receive differential signals and reference signals, with a reset mechanism and positive feedback latch to minimize offset voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If dynamic cross-coupled inverter latch is used, then power dissipation is reduced, but offset voltage increases significantly
Solution Approach 1:
The comparator is divided into two distinct phases: a first phase where reset transistors equalize the voltages at the gates of the latch transistors, and a second phase where the latch operates normally. This temporal segmentation allows the circuit to achieve low offset voltage during the first phase while maintaining low power dissipation during the second phase, resolving the contradiction between power efficiency and offset voltage performance.
Solution Approach 2:
Before the latch operation begins, reset transistors are activated to pre-equalize the voltages at the gates of the latch transistors. This preliminary action removes the offset voltage component before the main comparison operation, allowing the dynamic latch to operate with minimal offset while maintaining its low power characteristics.
2Measurement precision
If more capacitors are used, then measurement precision improves, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent removes the capacitors from the circuit entirely, replacing their voltage storage function with a timing-based approach using controlled transistor switching. The reset transistors hold the equalized voltage state during the first phase without requiring capacitive storage, thereby achieving accurate voltage comparison while eliminating the complexity and cost associated with multiple capacitors.
Solution Approach 2:
The patent replaces the passive capacitive voltage storage mechanism with an active transistor-based control mechanism. Instead of using capacitors to maintain voltage levels, the invention uses controlled transistor switching and timing phases to achieve the same functional outcome, thereby reducing device complexity while maintaining measurement precision.
3Ease of manufacture
If device mismatch increases to five percent, then manufacturing ease improves, but offset voltage increases
Solution Approach 1:
The reset transistors are activated before the latch operation to pre-compensate for device mismatches by equalizing the voltages at the gates of the latch transistors. This preliminary anti-action counteracts the effect of device mismatch before it can manifest as offset voltage, allowing the circuit to maintain low offset even when device mismatch increases to five percent, thereby improving manufacturing ease without sacrificing measurement precision.
Data Source
AI summary
A differential comparator is provided. The comparator receiving two differential signals and generating a comparison result represented by an output signal on one of two output terminals respectively on two current paths. The comparator comprises two pairs of latch transistors respectively disposed on the two current paths and two pairs of input transistors respectively disposed on the two current paths, wherein gates of the latch transistors on one of the current paths are commonly coupled to the output terminal between the latch transistors on the other current path, gates of the input transistors on one of the current paths respectively receives an input signal of one of the differential signals and a reference signal of the other differential signal and each of the input transistors is disposed between the output terminal and one of the latch transistors on the current path thereof.