Comparator Latch Circuit Using Capacitive Noise Cancellation

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Solution Overview

Problem

Comparator circuits using SR latch circuits face challenges in obtaining correct determination results when the potential difference between input signals is small, due to the influence of parasitic capacitance, leading to oscillation and reduced precision.

Innovation Solution

Incorporating capacitive elements connected between the input and output nodes of NAND or NOR circuits within the latch circuit to cancel out the noise generated by parasitic capacitance, thereby suppressing voltage changes and improving determination precision.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stability of the object's composition

If an SR latch circuit is used in a comparator circuit, then the circuit can maintain stable operation, but parasitic capacitance causes noise and oscillation when the potential difference between input signals is small

Engineering Contradiction:

Improvestable operationVSAvoiddetermination precision

Core Design Contradiction:

Stability of the object's compositionVSMeasurement precision

Solution Approach 1:

The patent introduces capacitive elements that generate noise opposite in phase to the noise from parasitic capacitance. This converts the harmful effect of parasitic capacitance into a beneficial cancellation effect, where the two noise sources neutralize each other, eliminating oscillation and enabling precise comparison even when input potential differences are small

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The capacitive elements are configured to produce counter-phase noise signals in advance, before the parasitic capacitance noise can cause oscillation. This preliminary anti-action prevents the harmful oscillation from occurring by having the opposing noise ready to cancel it out

Inventive Principle:

Principle #9Preliminary anti-action

2Device complexity

If parasitic capacitance is present in the latch circuit, then the circuit structure is simple, but noise and oscillation occur when input potential difference is small

Engineering Contradiction:

Improvecircuit structureVSAvoidcorrect determination result

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

Instead of removing the parasitic capacitance or adding complex shielding structures, the patent converts the harmful parasitic capacitance effect into a beneficial one by introducing capacitive elements that generate opposite-phase noise, achieving reliable operation while maintaining circuit simplicity

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

3Use of energy by moving object

If the potential difference between input signals is small, then energy consumption is reduced, but the comparator cannot obtain correct determination results due to noise interference

Engineering Contradiction:

Improveenergy consumptionVSAvoiddetermination precision

Core Design Contradiction:

Use of energy by moving objectVSMeasurement precision

Solution Approach 1:

The patent enables correct determination even with small input potential differences (low energy states) by converting the parasitic capacitance noise into beneficial counter-phase noise through the capacitive elements, allowing precise comparison without requiring large energy-driven signal differences

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed solution extends the operation area of the comparator circuit and enhances determination precision by reducing oscillation and noise interference, even when the potential difference between input signals is small.

Implementation Method 1

a first capacitive element, one end of which is connected to the first input node and the other end of which is connected to the output node of the first NAND circuit

Methodology Applied

Scientific EffectCapacitance: Capacitance

Data Source

PatentUS10454458B2Latch circuit and comparator circuit

Publication Date: 2019.10.22 KIOXIA CORP

AI summary

A latch circuit includes first and second NAND circuits and first and second capacitive elements. The first NAND circuit has a first input node into which a first signal is input. The second NAND circuit has a first input node into which a second signal is input, a second input node which is connected to an output node of the first NAND circuit, and an output node which is connected to a second input node of the first NAND circuit. The first capacitive element has one end connected to the first input node of the first NAND circuit and has another end connected to the output node of the first NAND circuit. The second capacitive element has one end connected to the first input node of the second NAND circuit and has another end connected to the output node of the second NAND circuit.