Comparator Level Holding Circuit for AD Conversion Noise Reduction
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Solution Overview
Problem
CMOS image sensors experience errors in AD conversion due to fluctuations in the consumption current of the comparator, leading to image quality degradation and streaking phenomena caused by power supply voltage fluctuations across comparators.
Innovation Solution
A comparator design incorporating a first amplifier with differential-pair transistors, a second amplifier for signal gain, and a level holding part to maintain a predetermined level, ensuring the current source transistor operates within a saturated condition, thereby reducing noise and errors in AD conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a comparator is used in a single-slope AD converter, then AD conversion can be performed by comparing ramp waves with input signals, but fluctuations in the comparator's consumption current cause power supply voltage fluctuations that lead to errors in AD conversion results
Solution Approach 1:
The clamp circuit is configured to clamp the potential of the first output node before the inversion of the comparator output, preventing the consumption current fluctuation from occurring in the first place. This preliminary action stabilizes the power supply voltage before it can cause errors in other AD converters.
Solution Approach 2:
The clamp circuit acts as an intermediary between the comparator and the power supply, isolating the power supply from the consumption current fluctuations. By clamping the output node potential, it mediates the interaction between the comparator's switching action and the power supply voltage, preventing noise propagation to other AD converters.
2Adaptability or versatility
If multiple AD converters share common ramp waves, then resource utilization is improved, but the comparator's current fluctuations affect other AD converters causing streaking phenomena in images
Solution Approach 1:
The harmful effect of consumption current fluctuation is extracted and contained at the output node of the affected comparator by using the clamp circuit. This isolates the noise source, preventing it from propagating to the power supply and affecting other AD converters that share the common ramp waves.
Solution Approach 2:
The inversion of the comparator output, which originally causes harmful current fluctuations, is converted into a beneficial trigger for the clamp circuit. The clamp circuit detects the inversion and responds by clamping the output node potential, transforming the harmful switching action into a controlled event that stabilizes the power supply voltage.
3Ease of operation
If the output node potential fluctuates during comparator operation, then the comparator can function, but the power supply voltage fluctuates causing errors in AD conversion
Solution Approach 1:
The clamp circuit performs preliminary clamping of the output node potential before the comparator's consumption current fluctuation can propagate to the power supply. This preliminary stabilization ensures that the power supply voltage remains stable even as the comparator operates and its output inverts.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces noise and improves AD converter precision, minimizing image quality degradation and streaking issues by stabilizing the power supply voltage across comparators.
Implementation Method 1
The first amplifier includes differential-pair transistors and outputs a signal of a level corresponding to a comparison result from a first output node. The differential-pair transistors function as a comparison part that compares a reference voltage with a potential of an input signal.
Implementation Method 2
The second amplifier amplifies a signal output from the first output node of the first amplifier and outputs the signal from a second output node.
Implementation Method 3
The level holding part holds a level of the second output node at a predetermined level. The level holding part holds the level of the second output node of the second amplifier such that the transistor for the current source of the second amplifier does not fall into a level at which a saturated operation condition is not satisfied.
Data Source
AI summary
A comparator includes a first amplifier, a second amplifier, and a level holding part. The first amplifier includes differential-pair transistors and outputs a signal of a level corresponding to a comparison result from a first output node. The differential-pair transistors compare a reference voltage with a potential of an input signal. The second amplifier gain up the signal output from the first output node of the first amplifier and outputs the signal from a second output node. The level holding part holds a level of the second output node at a predetermined level. The second amplifier includes a transistor for amplification and a transistor for a current source. The level holding part holds the level of the second output node of the second amplifier such that the transistor for the current source does not fall into a level at which a saturated operation condition is not satisfied.