Comparator Circuit Topology for Low-Voltage Wide-Range Sensing

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Solution Overview

Problem

Existing comparator circuits face limitations in operating at low supply voltage and high common mode input range while consuming low current, as they often have limited voltage range due to diode transistors' voltage drops, leading to reduced gain and accuracy in detecting small voltage differences.

Innovation Solution

The electronic comparator circuit design includes input transistors connected in a differential configuration with gain transistors having higher transconductance, allowing for a larger voltage range and increased gain, enabling operation at low supply voltage (down to 0.6 V) and high common mode input range (approximately 0.6 V) while consuming low current (50 nA).

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If diode transistors are used in conventional comparator circuits, then the circuit structure is simple, but the voltage range is limited due to voltage drops across the diode transistors

Engineering Contradiction:
Improvecircuit structureVSAvoidvoltage range
Core Design Contradiction:
Device complexityVSEase of operation

Solution Approach 1:

The patent divides the single diode transistor connection into separate components: a third transistor and a fourth transistor connected in series, where the fourth transistor is in diode configuration. This segmentation allows the first terminal of the first input transistor to be connected at the same voltage as the first terminal of the third transistor, effectively increasing the voltage range while maintaining structural simplicity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different configurations to different transistors: the fourth transistor is specifically connected in diode configuration while the third transistor is connected in a different manner. This local differentiation optimizes the voltage range for the input stage while maintaining the simplicity of the diode connection where needed.

Inventive Principle:
Principle #3Local quality

2Measurement precision

If gain transistors with higher transconductance are used, then the gain on output voltage is increased, but the device complexity increases

Engineering Contradiction:
ImprovegainVSAvoidtransistor configuration
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent combines the gain function with the existing transistor structure by cross-coupling the gates of the gain transistors (seventh and eighth) with the gates of the input stage transistors (fifth and third). This merging approach increases gain without adding completely separate gain stages, thereby limiting the increase in device complexity.

Inventive Principle:
Principle #5Merging (Combining)

3Use of energy by moving object

If the circuit is designed for low supply voltage operation, then power consumption is reduced, but the voltage range for accurate comparison is limited

Engineering Contradiction:
Improvepower consumptionVSAvoidcommon mode input range
Core Design Contradiction:
Use of energy by moving objectVSEase of operation

Solution Approach 1:

The patent extends the common mode input range by utilizing the series connection of the third and fifth transistors, which creates additional voltage headroom. This dimensional change in the circuit topology allows the circuit to operate accurately at low supply voltages (down to 0.6V) while maintaining a wide common mode input range (approximately 0.6V), thus resolving the contradiction between low power consumption and adequate voltage range.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20240421787A1Electronic comparator circuit
Publication Date: 2024.12.19 NORDIC SEMICONDUCTOR
  • US20240421787A1 patent drawing
  • US20240421787A1 patent drawing
  • US20240421787A1 patent drawing

AI summary

An electronic comparator circuit, including an input portion, an output portion, a first portion, a second portion and a gain portion. The input portion includes a first input transistor and a second input transistor. In the first portion a first terminal of a first input transistor is connected between a first terminal of a third transistor and a second terminal of a fourth transistor, wherein the fourth transistor is connected in a diode configuration. The second portion includes a first terminal of a second input transistor connected between a first terminal of a fifth transistor and a second terminal of a sixth transistor, wherein the sixth transistor is connected in a diode configuration. The gain portion includes a gate of a seventh gain transistor cross-coupled to a gate of the fifth transistor. A gate of an eighth gain transistor is cross-coupled to a gate of the third transistor.